Shift register unit, driving method, gate driving circuit, and display device

By designing the circuit structure of the shift register unit, the problems of signal competition and instability in the row driving technology of the array substrate were solved, realizing high reliability and efficient production of the display panel, supporting forward and reverse scanning, and reducing the complexity of the manufacturing process.

WO2025213361A1 Publication Date: 2025-10-16BOE TECHNOLOGY GROUP CO LTD +1
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Patent Information

Application Number
PCT/CN2024/086816
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-04-09
Publication Date
2025-10-16

AI Technical Summary

Technical Problem

In the prior art, when integrating thin-film transistor gate switching circuits on a display panel using array substrate gate drive (GOA) technology, there are signal competition and instability issues, which affect the reliability and production capacity of the display panel.

Method used

A shift register unit is designed. Through the mutual cooperation of the first input circuit, the second input circuit, the first control circuit, the second control circuit and the output circuit, the level stability of the node signal is ensured, competition is avoided, the output stability is improved, and the forward and reverse scanning functions are realized through the cascade circuit.

Benefits of technology

The reliability and output stability of the shift register unit are improved, the forward and reverse scanning functions are realized, the complexity of the preparation process is reduced, and the production efficiency and yield of the display panel are improved.

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Abstract

A shift register unit, a driving method, a gate driving circuit, and a display device. The shift register unit comprises: a first input circuit (10) configured to provide a signal of a first reference voltage signal end (VREF1) to a first node (N1) in response to a signal of an input signal end (IPT); a second input circuit (20) configured to provide a signal of a second reference voltage signal end (VREF2) to the first node (N1) in response to a signal of a reset signal end (RST); a first control circuit (30) configured to control the level of a signal of the first node (N1) to be opposite to that of a second node (N2); a second control circuit (40) coupled to the second node (N2) and configured to provide a signal of a third reference voltage signal end (VREF3) to the second node (N2) in response to the signal of the input signal end (IPT) and a signal of an output signal end (OPT); and an output circuit (50) coupled to the first node (N1) and the second node (N2), and configured to provide a signal of a clock signal end (CLK) to the output signal end (OPT) in response to the signal of the first node (N1), and provide the signal of the third reference voltage signal end (VREF3) to the output signal end (OPT) in response to the signal of the second node (N2).
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