Data processing method, apparatus and system

Abstract

Disclosed in the embodiments of the present application are a data processing method, apparatus and system. The method comprises: performing p:q symbol demultiplexing, alignment marker locking and deskewing on p first data streams which have been subjected to Reed-Solomon (RS) encoding, so as to obtain q second data streams, wherein p is an integer greater than or equal to 1, and q is greater than p and is an integer multiple of p; respectively performing 1:n block distribution on the q second data streams, so as to obtain m third data streams, wherein m=n×q, and n is an integer greater than 1; and respectively performing convolutional interleaving on the m third data streams, so as to obtain m interleaved data streams. Therefore, outer-code symbol boundaries can be acquired before inner-code encoding, and low-latency and low-complexity interleaving is used, so as to achieve a better concatenated forward error correction (FEC) performance; thus, the present application can be applied to more transmission scenarios.

Description

A data processing method, apparatus and system

[0001] This application claims priority to Chinese patent application filed on December 13, 2024, with application number 202411848981.5 and entitled "A Data Processing Method, Apparatus and System", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by technologies such as 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards high capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. Forward error correction (FEC) coding is used to correct transmission errors, allowing the receiver to recover the original data sent by the transmitter from the received data. A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via a connection unit interface. The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, modulates the bit sequence resulting from the second FEC encoding to generate a corresponding modulation symbol sequence, and finally generates an optical signal based on the modulation symbol sequence, which is transmitted to the receiver via optical fiber. The first FEC encoding is also called external code encoding, and the second FEC encoding is also called internal code encoding. The modulation mapping is also called symbol mapping.

[0004] For coherent transmission scenarios, existing technical solutions provide cascaded FEC schemes for 800G transmission scenarios, but not for 1.6T transmission scenarios. Existing cascaded FEC schemes for 800G transmission scenarios cannot be directly applied to 1.6T transmission scenarios. More specifically, the client sublayer, a 1.6TBASE-R 8:8 Physical Media Attachment (PMA) based on symbol-multiplexing (SM), also known as 1.6TBASE-R 8:8SM-PMA, does not provide symbol boundaries, which affects the error correction performance of the overall cascaded FEC scheme. Furthermore, the skew of the eight data streams output by 1.6TBASE-R 8:8SM-PMA also affects the error correction performance of the overall cascaded FEC scheme. For a solution using the 1.6TBASE-R 8:16SM-PMA client sublayer, the skewness of the 16 data streams output by 1.6TBASE-R 8:16SM-PMA can affect the error correction performance of the overall cascaded FEC solution. Furthermore, the interleaving scheme in current cascaded FEC solutions designed for 800G transmission scenarios cannot be directly applied to 1.6T service transmission. Therefore, how to obtain symbol boundaries, remove skewness, and employ low-complexity and low-latency interleaving to optimize the overall cascaded error correction performance is a critical issue that 1.6T coherent transmission solutions urgently need to address. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system that enables the outer code symbol boundary to be obtained before the inner code is encoded, and employs low latency and low complexity interleaving to achieve superior cascaded FEC error correction performance, which can be applied to a wide range of transmission scenarios.

[0006] In a first aspect, embodiments of this application provide a data processing method, comprising: performing p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams, wherein p is an integer greater than or equal to 1, and q is greater than p and an integer multiple of p; distributing the q second data streams into 1:n blocks to obtain m third data streams, wherein m = n × q, and n is an integer greater than 1; and performing convolutional interleaving on the m third data streams to obtain m interleaved data streams. In this embodiment, the q second data streams are distributed before convolutional interleaving, which can reduce the throughput of each convolutional interleaving path and thus reduce the difficulty of hardware implementation, making it particularly suitable for transmission scenarios of 1.6T and higher speeds.

[0007] In conjunction with the first aspect, in a first possible implementation of the first aspect, after obtaining m interleaved data streams, the method further includes: performing data processing on the m interleaved data streams, including internal code encoding and dual polarization symbol mapping, to obtain one dual polarization data stream.

[0008] In conjunction with the first aspect and the first possible implementation of the first aspect, in the second possible implementation of the first aspect, the step of distributing the q second data streams in a 1:n block manner to obtain m third data streams specifically includes: distributing each second data stream in a round-robin manner with h RS symbols as the granularity to obtain n third data streams, for a total of n×q third data streams, where h is an integer greater than or equal to 1, and each RS symbol includes 10 bits.

[0009] It should be understood that the embodiments in the specification use the example of distributing t RS-FEC four symbols each time to explain the distribution. In this case, h = 4 × t. If t = 1, then h = 4, that is, 4 symbols (40 bits) are distributed each time. Optionally, h is a positive integer multiple of 4. This allows the four consecutive RS symbols of the third data stream to come from four RS codewords, thereby reducing the latency of convolutional interleaving.

[0010] In conjunction with the first aspect and any possible implementation thereof, in a third possible implementation of the first aspect, n is 2, 4, or 8, and h is 4 or 8. In this embodiment, n and h can be arbitrarily combined, for example, n = 2, h = 4; or n = 4, h = 4; or n = 2, h = 8, etc., and this application does not impose any limitation. This facilitates matching the processing bit width of specific hardware implementations, making hardware implementation simpler.

[0011] In conjunction with the first aspect and any possible implementation thereof, in the fourth possible implementation thereof, q = s × p, where s is 2, 4 or 8.

[0012] In conjunction with the first aspect and any possible implementation thereof, in the fifth possible implementation of the first aspect, the p:q symbol demultiplexing includes p 1:s symbol demultiplexings, wherein each of the p 1:s symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides a specific implementation method for demultiplexing, which is simple to implement.

[0013] In conjunction with the fifth possible implementation of the first aspect, in the sixth possible implementation of the first aspect, the 1:s symbol demultiplexing employs a polling method that distributes 40 bits at a time to demultiplex the corresponding first data stream to obtain s fourth data streams. It should be understood that using a 40-bit polling method can match the four-symbol boundaries, which is used to lock the alignment identifier for each fourth data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0014] In conjunction with the sixth possible implementation of the first aspect, in the seventh possible implementation of the first aspect, if at least one of the s fourth data streams fails to achieve alignment identifier locking within a threshold time interval, the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is shifted, and 1:s symbol demultiplexing is performed again to re-obtain the s fourth data streams; alignment identifier locking is then performed on each of the re-obtained s fourth data streams. This embodiment provides a complete process for obtaining the four-symbol boundaries; only when all fourth data streams achieve alignment identifier locking can the correct four-symbol boundaries be obtained.

[0015] In conjunction with the seventh possible implementation of the first aspect, in the eighth possible implementation of the first aspect, the granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 1 bit; or, the granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities, which can be matched to the specific hardware implementation processing bit width, making implementation relatively simple and with low complexity.

[0016] In conjunction with the first aspect and any possible implementation thereof, in the ninth possible implementation of the first aspect, the codeword length of the internal code is 126 bits, wherein 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, wherein 120 bits are information bits and 8 bits are parity bits. In the embodiments of this application, regardless of the internal code used, p = 8, q = 16, or p = 4, q = 16.

[0017] In conjunction with the first aspect and any possible implementation thereof, in the tenth possible implementation thereof, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits.

[0018] In conjunction with the first aspect and any possible implementation thereof, in the eleventh possible implementation of the first aspect, the convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0019] In conjunction with the eleventh possible implementation of the first aspect, in the twelfth possible implementation of the first aspect, each delay line receives 40 bits as input and outputs 40 bits at a time. The continuous r×40 bits in the output data stream after convolutional interleaving include the 40 bits output from each delay line. The 40 bits stored in the storage unit are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaver come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0020] In conjunction with the eleventh or twelfth possible implementation of the first aspect, in the thirteenth possible implementation of the first aspect, m = 4 × q; the delay line with the largest sequence number among the r delay lines includes 0 storage units, or the delay line with the smallest sequence number among the r delay lines includes 0 storage units; r = 3, Q ≥ 4; or, m = 2 × q; the delay line with the largest sequence number among the r delay lines includes 0 storage units, r = 3, Q ≥ 7; or, m = 2 × q; the delay line with the smallest sequence number among the r delay lines includes 0 storage units, r = 3, Q ≥ 6. The several possibilities given in this embodiment can all guarantee that the 12 consecutive RS symbols output by the convolutional interleaver come from 12 different RS codewords, enabling the cascaded FEC to have good decoding performance; moreover, the convolutional interleaving delay is small, thus resulting in a small system delay, making it suitable for a wider range of transmission scenarios.

[0021] In conjunction with the first aspect and any possible implementation thereof, in the fourteenth possible implementation of the first aspect, there is no skew between any two of the q second data streams; or, there is a d skew between any two of the q second data streams. skew The skewness of bits, where d skew It must be an integer multiple of 40. In this case, the deskewing process can also be called 40-bit deskewing.

[0022] In conjunction with any possible implementation of the first aspect, in the fifteenth possible implementation of the first aspect, the dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

[0023] Secondly, embodiments of this application provide a data processing apparatus, including: a first processing unit and a second processing unit; the first processing unit is used to perform p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS, to obtain q second data streams, where p is an integer greater than or equal to 1, and q is greater than p and an integer multiple of p; the second processing unit is used to perform 1:n block distribution on the q second data streams respectively, to obtain m third data streams, where m = n × q, and n is an integer greater than 1; and to perform convolutional interleaving on the m third data streams respectively, to obtain m interleaved data streams. In this embodiment of the application, the q second data streams are distributed separately before performing convolutional interleaving, which can reduce the throughput of each convolutional interleaving path and thus reduce the difficulty of hardware implementation, and is particularly suitable for transmission scenarios of 1.6T and higher speeds.

[0024] In conjunction with the second aspect, in a first possible implementation of the second aspect, the second processing unit is further configured to perform data processing on the m interleaved data streams, including internal code encoding and dual polarization symbol mapping, to obtain a single dual polarization data stream.

[0025] In conjunction with the second aspect and the first possible implementation of the second aspect, in the second possible implementation of the second aspect, the second processing unit is specifically used to: distribute each second data stream in a round-robin manner with h RS symbols as the granularity to obtain n third data streams, for a total of n×q third data streams, where h is an integer greater than or equal to 1, and each RS symbol includes 10 bits.

[0026] It should be understood that the embodiments in the specification use the example of distributing t RS-FEC four symbols each time to explain the distribution. In this case, h = 4 × t. If t = 1, then h = 4, that is, 4 symbols (40 bits) are distributed each time. Optionally, h is a positive integer multiple of 4. This allows the four consecutive RS symbols of the third data stream to come from four RS codewords, thereby reducing the latency of convolutional interleaving.

[0027] In conjunction with the second aspect and any possible implementation thereof, in a third possible implementation of the second aspect, n is 2, 4, or 8, and h is 4 or 8. In this embodiment, n and h can be arbitrarily combined, for example, n = 2, h = 4; or n = 4, h = 4; or n = 2, h = 8, etc., and this application does not impose any limitation. This facilitates matching the processing bit width of specific hardware implementations, making hardware implementation simpler.

[0028] In conjunction with the second aspect and any possible implementation thereof, in the fourth possible implementation thereof, q = s × p, where s is 2, 4 or 8.

[0029] In conjunction with the second aspect and any possible implementation thereof, in the fifth possible implementation of the second aspect, the p:q symbol demultiplexing includes p 1:s symbol demultiplexings, wherein each of the p 1:s symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides a specific implementation method for demultiplexing, which is simple to implement.

[0030] In conjunction with the fifth possible implementation of the second aspect, in the sixth possible implementation of the second aspect, the 1:s symbol demultiplexing employs a polling method that distributes 40 bits at a time to demultiplex the corresponding first data stream to obtain s fourth data streams. It should be understood that using a 40-bit polling method can match the four-symbol boundaries, which is used to lock the alignment identifier for each fourth data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0031] In conjunction with the sixth possible implementation of the second aspect, in the seventh possible implementation of the second aspect, if at least one of the s fourth data streams fails to achieve alignment identifier locking within a threshold time interval, the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:s symbol demultiplexing, and re-perform 1:s symbol demultiplexing to re-obtain the s fourth data streams; and perform alignment identifier locking on each of the re-obtained s fourth data streams. This embodiment provides a complete process for obtaining the four-symbol boundaries; only when all fourth data streams achieve alignment identifier locking can the correct four-symbol boundaries be obtained.

[0032] In conjunction with the seventh possible implementation of the second aspect, in the eighth possible implementation of the second aspect, the granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 1 bit; or, the granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities, which can be matched to the specific hardware implementation processing bit width, making implementation relatively simple and with low complexity.

[0033] In conjunction with the second aspect and any possible implementation thereof, in the ninth possible implementation of the second aspect, the codeword length of the internal code is 126 bits, wherein 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, wherein 120 bits are information bits and 8 bits are parity bits. In the embodiments of this application, regardless of the internal code used, p = 8, q = 16, or p = 4, q = 16.

[0034] In conjunction with the second aspect and any possible implementation thereof, in the tenth possible implementation of the second aspect, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits.

[0035] In conjunction with the second aspect and any possible implementation thereof, in the eleventh possible implementation of the second aspect, the convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0036] In conjunction with the eleventh possible implementation of the second aspect, in the twelfth possible implementation of the second aspect, each delay line receives 40 bits as input and outputs 40 bits at a time. The continuous r×40 bits in the output data stream after convolutional interleaving include the 40 bits output from each delay line. The 40 bits stored in the storage unit are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaver come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0037] In conjunction with the eleventh or twelfth possible implementation of the second aspect, in the thirteenth possible implementation of the second aspect, m = 4 × q; the delay line with the largest sequence number among the r delay lines includes 0 storage units, or the delay line with the smallest sequence number among the r delay lines includes 0 storage units; r = 3, Q ≥ 4; or, m = 2 × q; the delay line with the largest sequence number among the r delay lines includes 0 storage units, r = 3, Q ≥ 7; or, m = 2 × q; the delay line with the smallest sequence number among the r delay lines includes 0 storage units, r = 3, Q ≥ 6. The several possibilities given in this embodiment can all guarantee that the 12 consecutive RS symbols output by the convolutional interleaver come from 12 different RS codewords, enabling the cascaded FEC to have good decoding performance; moreover, the convolutional interleaving delay is small, thus resulting in a small system delay, making it suitable for a wider range of transmission scenarios.

[0038] In conjunction with the second aspect and any possible implementation thereof, in the fourteenth possible implementation of the second aspect, there is no skew between any two of the q second data streams; or, there is a d skew between any two of the q second data streams. skew The skewness of bits, where d skew It must be an integer multiple of 40. In this case, the deskewing can also be called 40-bit deskewing.

[0039] In conjunction with any possible implementation of the second aspect, in the fifteenth possible implementation of the second aspect, the dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

[0040] Thirdly, embodiments of this application provide a chip for performing the methods described in the first aspect or any of the embodiments in the first aspect.

[0041] Fourthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in the first aspect or any embodiment of the first aspect, and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0042] Fifthly, embodiments of this application provide a communication device. The communication device includes a host-side device and an optical module as described in the fourth aspect or any embodiment thereof, the optical module being connected to the host-side device.

[0043] Sixthly, embodiments of this application provide another device. This device includes a processor and an interface. The processor is used to perform the methods described in the first aspect or any embodiment of the first aspect, and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The device may be a router, switch, server, or optical transport network equipment, etc.

[0044] In a seventh aspect, embodiments of this application provide a communication system, which includes a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is a communication device as described in the fifth aspect or any embodiment of the fifth aspect, and the first communication device and the second communication device are connected.

[0045] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in the first aspect or any embodiment of the first aspect to be implemented.

[0046] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the method described in the first aspect or any of the embodiments described in the first aspect. Attached Figure Description

[0047] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0048] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0049] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0050] Figure 4 is a flowchart of a data processing method provided in an embodiment of this application;

[0051] Figure 5(a) is a flowchart of an embodiment of this application for obtaining multiple de-skewed data streams;

[0052] Figure 5(b) is a flowchart illustrating a specific method for acquiring multiple de-skewed data streams according to an embodiment of this application.

[0053] Figure 5(c) is a flowchart of another specific process for obtaining multiple de-skewed data streams provided in an embodiment of this application;

[0054] Figure 6(a) is a schematic diagram of a deskewing method provided in an embodiment of this application;

[0055] Figure 6(b) is a schematic diagram of another deskewing method provided in an embodiment of this application;

[0056] Figure 7(a) is a schematic diagram of block distribution provided in an embodiment of this application;

[0057] Figure 7(b) is a schematic diagram of another block distribution provided by an embodiment of this application;

[0058] Figure 7(c) is a schematic diagram of another block distribution provided in an embodiment of this application;

[0059] Figure 8(a) is a schematic diagram of a convolutional interleaving process provided in an embodiment of this application;

[0060] Figure 8(b) is a schematic diagram of another convolutional interleaving process provided in an embodiment of this application;

[0061] Figure 9 is a schematic diagram of a data processing architecture provided in this application;

[0062] Figure 10 is a schematic diagram of a cyclic shift provided in this application;

[0063] Figure 11 is a schematic diagram of another data processing architecture provided in this application;

[0064] Figure 12 is a schematic diagram of another type of cyclic shift provided in this application;

[0065] Figure 13 is a schematic diagram of another data processing architecture provided in this application;

[0066] Figure 14 is a schematic diagram of the structure of a data processing device provided in this application;

[0067] Figure 15 is a structural schematic diagram of an optical module provided in this application;

[0068] Figure 16 is a schematic diagram of the structure of a communication device provided in this application. Detailed Implementation

[0069] This application provides a data processing method, apparatus, and system that enables the outer code symbol boundary to be obtained before the inner code is encoded, and employs low latency and low complexity interleaving to achieve superior cascaded FEC error correction performance, which can be applied to a wide range of transmission scenarios.

[0070] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0071] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device located at the transmitting end, and the receiving device 05 is also called a client device located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The transmitting end processing module 02 and the receiving end processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be a ZR optical module, FR optical module, or LR optical module, such as a 1.6T FR1 coherent optical module (referred to as a 1.6T FR coherent optical module), a 1.6T LR1 coherent optical module (referred to as a 1.6T LR coherent optical module), or a 1.6T ZR coherent optical module. Furthermore, the transmitting end device 01, transmitting end processing module 02, channel transmission medium 03, receiving end processing module 04, and receiving end device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0072] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, during the data transmission process from the transmitting device 01 to the receiving device 05, the transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to the transmitting processing module 02. The transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits the data with both external and internal code encoding to the channel transmission medium 03. The channel transmission medium 03 transmits the data with both external and internal code encoding to the receiving processing module 04. The receiving processing module 04 performs internal code decoding on the data with both external and internal code encoding and transmits the internally decoded data to the receiving device 05. The receiving device 05 performs external code decoding on the data with internal code decoding.

[0073] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external encoding methods described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use Reed-Solomon (RS) code for external encoding, and the transmitting processing module 02 can use Hamming code for internal encoding. Alternatively, the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal encoding. A BCH code correcting a single error is equivalent to a Hamming code. Another example is that the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can also use Polar code for internal encoding. In some specific application scenarios, the transmitting device 01 can use RS(544,514) code, also known as KP4 code, for external encoding.

[0074] Figure 3 is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 3, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The data after external code encoding and internal code encoding is sent to the transmission medium 03. The receiving device 05 decodes the internal code and external code of the data received from the transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device or host device located at the transmitting end, and the receiving device 05 is also called a client chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device includes a client chip and an interface. The client chip is also called a host chip. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission, which is not limited here. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In this case, the transmitting device 01 can also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0075] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0076] Figure 4 is a schematic flowchart of a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied to the sending end, for example, it can be implemented by the sending end processing module 02 shown in Figure 2 above, or by the sending end device 01 shown in Figure 3 above.

[0077] 101. Perform p:q symbol demultiplexing, alignment identifier locking, and deskewing on the p first data streams encoded by RS to obtain q second data streams, where p is an integer greater than or equal to 1, and q is greater than p and is an integer multiple of p.

[0078] Specifically, q can be an even multiple of p, for example, q = 2 × p, q = 4 × p, or q = 8 × p.

[0079] In this embodiment, all p first data streams are data streams encoded with external codes. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding, such as BCH encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS code is counted in units of symbols. The symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, that is, the codeword of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a in each first data stream RS The adjacent RS symbols are respectively from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2.

[0080] In some specific applications, targeting 1.6T transmission scenarios, such as 1.6TBASE-R transmission, consider p=8. The nominal rate of each of the p=8 first data streams is 212.5 Gbits per second (b / s). In some specific applications, the p=8 first data streams are obtained by demodulating 8 AUI data streams from 1.6T AUI-8 using 4-Level Pulse Amplitude Modulation (PAM4). This PAM4 demodulation is also called PAM4 decoding. The 8 AUI data streams from 1.6T AUI-8 are obtained by processing 16 Physical Coding Sublayer lane (PCSL) data streams using 1.6TBASE-R 16:8SM-PMA. In each of the 16 PCSL data streams, every four adjacent RS symbols come from four RS codewords.

[0081] In other specific applications, targeting 1.6T transmission scenarios, such as 1.6TBASE-R transmission, consider p=4. The nominal rate of each of the p=4 first data streams is 425.0 Gbits per second (b / s). In some specific applications, the p=4 first data streams are obtained by demodulating four AUI data streams of 1.6TBASE-4 using four-level pulse amplitude modulation (PAM4). This PAM4 demodulation is also called PAM4 decoding. The four AUI data streams of 1.6TBASE-4 are obtained by processing 16 PCSL data streams using 1.6TBASE-R 16:4SM-PMA. In each of the 16 PCSL data streams, every four adjacent RS symbols come from four different RS codewords.

[0082] As shown in Figure 5(a), p:q symbol demultiplexing is performed on the p first data streams to obtain q second data streams. The cases of q = 2 × p and q = 4 × p are described below.

[0083] 1) For the case where q = 2 × p:

[0084] As shown in Figure 5(b), the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, each corresponding one-to-one with a p first data stream. Each 1:2 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex its input first data stream, resulting in two output demultiplexed data streams. It is understood that the granularity of the round-robin can be more or less, for example, 20 bits, 60 bits, 80 bits, etc., and this application does not impose any limitations.

[0085] The q-strip demultiplexed data streams are each subjected to alignment marker lock processing. Here, alignment marker lock is also simply referred to as alignment lock. The alignment marker lock operation utilizes the known alignment marker (AM) in the PCSL data stream.

[0086] Alignment identifier locking can only be achieved in the two output demultiplexed data streams if and only if 40 bits are distributed in the 1:2 symbol demultiplexing process corresponding to 4 symbols (i.e., 4 foreign code RS symbols), that is, the 40-bit boundary corresponds to 4 symbol boundaries. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked, at which point an RS codeword boundary is obtained. The boundary of the 40 distributed bits is a four-symbol boundary. It should be understood that each first data stream has its own four-symbol boundary and RS codeword boundary.

[0087] Within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222, 822, 400 bits), when the two output demultiplexed data streams do not achieve alignment identifier locking, the 40-bit boundary distributed in the above 1:2 symbol demultiplexing is shifted. This shift is also called slipping. In some specific applications, the 40-bit boundary distributed in the above 1:2 symbol demultiplexing is slipped by 1 bit. In other specific applications, the 40-bit boundary distributed in the above 1:2 symbol demultiplexing is slipped by a bit greater than 1, such as 2 bits, 3 bits, etc.; in addition, to ensure that all possible boundaries are evaluated, 40×m+1 bits can also be slipped, where m is an integer greater than 0, such as 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's processing bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until the alignment flag lock is achieved for all two demultiplexed data streams of the 1:2 symbol demultiplexed output. When both demultiplexed data streams of the 1:2 symbol demultiplexed output achieve alignment flag lock, four-symbol lock is achieved, and the four-symbol boundary corresponding to the first data stream is obtained. Then, a deskew operation is performed on the locked data stream.

[0088] The deskewing process is also called de-offsetting. In some specific applications, deskewing is performed on the q locked data streams so that there is no skew between the q second data streams after deskewing. That is, as shown in Figure 6(a), the start bits of the alignment flags of all q second data streams are aligned and there is no time offset, in order to support the accurate calculation of possible path data delay. In this case, the deskewing is also called full deskewing. In other specific applications, the deskewing is based on 40-bit deskewing, that is, it allows a d-bit difference between any two data streams in the q second data streams after deskewing. skewThe skewness of a bit, i.e., as shown in Figure 6(b), means that the start bit of the alignment flag in any two demultiplexed data sets may have a skewness of d bits. skew A bit time offset. Where d skew When the value is a multiple of 40, the deskewing is also called 40-bit deskewing.

[0089] 2) For the case where q = 4 × p:

[0090] As shown in Figure 5(c), the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, and each of the p 1:4 symbol demultiplexings corresponds one-to-one with a p first data stream. Each 1:4 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex the input first data stream into four output demultiplexed data streams.

[0091] The q-strip demultiplexed data streams are each subjected to alignment marker lock processing. Here, alignment marker lock is also simply referred to as alignment lock. The alignment marker lock operation utilizes the known alignment marker (AM) in the PCSL data stream.

[0092] Alignment identifier locking can only be achieved in the four output demultiplexed data streams if and only when 40 bits are distributed in the 1:4 symbol demultiplexing process corresponding to 4 symbols (i.e., 4 foreign code RS symbols), that is, the 40-bit boundary corresponds to 4 symbol boundaries. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked, at which point an RS codeword boundary is obtained. At this time, the boundary of the 40 distributed bits is a four-symbol boundary. It should be understood that each first data stream has its own four-symbol boundary and RS codeword boundary.

[0093] Within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222, 822, 400 bits), when the four output demultiplexed data streams do not achieve alignment identifier locking, the 40-bit boundary distributed in the above 1:4 symbol demultiplexing is shifted. This shift is also called slipping. In some specific applications, the 40-bit boundary distributed in the above 1:4 symbol demultiplexing is slipped by 1 bit. In other specific applications, the 40-bit boundary distributed in the above 1:4 symbol demultiplexing is slipped by a bit greater than 1, such as 2 bits, 3 bits, etc.; in addition, to ensure that all possible boundaries are evaluated, 40×m+1 bits can also be slipped, where m is an integer greater than 0, for example, 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's processing bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until all four demultiplexed data streams of the 1:4 symbol demultiplexed output achieve alignment flag locking. When all four demultiplexed data streams of the 1:4 symbol demultiplexed output achieve alignment flag locking, four-symbol locking is achieved, and the four-symbol boundary corresponding to the first data stream is obtained. Then, a deskewing operation is performed on the locked data stream.

[0094] The deskewing process is also called de-offsetting. In some specific applications, deskewing is performed on the q locked data streams so that there is no skew between the q second data streams after deskewing. That is, as shown in Figure 6(a), the start bits of the alignment flags of all q second data streams are aligned and there is no time offset, in order to support the accurate calculation of possible path data delay. In this case, the deskewing is also called full deskewing. In other specific applications, the deskewing is based on 40-bit deskewing, that is, it allows a d-bit difference between any two data streams in the q second data streams after deskewing. skew The skewness of a bit, i.e., as shown in Figure 6(b), means that the start bit of the alignment flag in any two demultiplexed data sets may have a skewness of d bits. skew A bit time offset. Where d skew When the value is a multiple of 40, the deskewing is also called 40-bit deskewing.

[0095] For the cases q = 2 × p and q = 4 × p, when all q demultiplexed data streams achieve alignment identifier locking, symbol-quartet locking is also achieved, and the four outer code symbol boundaries corresponding to each first data stream are also obtained. These four outer code symbol boundaries are also called symbol-quartet boundaries, or simply symbol boundaries. Since the second data stream is obtained by distributing the first data stream through four symbols, obtaining the four symbol boundaries of each first data stream also means obtaining the four symbol boundaries of each second data stream. At this point, the q second data streams are q PCSL data streams. The four adjacent RS symbols in the q second data streams come from four RS codewords. More specifically, for a second data stream, starting from the alignment identifier, the symbols in the data stream are represented in the form A, B, C, D, A, B, C, D… etc., where A, B, C, and D represent one RS symbol from four different codewords.

[0096] It should be noted that for the case of q = 8 × p, p 1:8 symbol demultiplexing and the same alignment identifier locking and deskewing processing as in the cases of q = 2 × p and q = 4 × p can be used to obtain q second data streams, which will not be elaborated here.

[0097] It should be noted that for 1.6T transmission scenarios, such as 1.6TBASE-R transmission, q=16.

[0098] It should be noted that in each of the first data streams, every four adjacent RS symbols come from four RS codewords. By obtaining the four-symbol boundary corresponding to a first data stream, the four adjacent RS symbols in the first data stream can also be obtained.

[0099] 102. Perform a 1:n block distribution on each of the q second data streams to obtain m third data streams, where m = n × q, and n is an integer greater than 1.

[0100] Specifically, 1:n block distribution can also be simply referred to as 1:n distribution; the value of n can be 2, 4, or 8.

[0101] Based on the obtained four-symbol boundaries, 40 adjacent (also called consecutive) bits in each second data stream can be obtained, corresponding to 4 RS symbols. More specifically, the 4 RS symbols come from 4 RS codewords. The 4 RS symbols are also called RS-FEC symbol quartets. Based on the four-symbol boundaries, each second data stream is distributed in a 1:n block ratio to obtain n third data streams, resulting in a total of m = n × q third data streams. A round-robin method is used to distribute t RS-FEC symbol quartets at a time. Figure 7(a) shows an implementation of a 1:2 block distribution of a second data stream to obtain two third data streams. Each distribution is t = 1 RS-FEC symbol-quartet. A, B, C, and D in the figure are consistent with the previous definition, representing one RS symbol from four different codewords. Together, they form an RS-FEC symbol, which consists of 10 bits, for a total of 40 bits. As can be seen from the figure, after the 1:2 block distribution shown in Figure 7(a), four consecutive symbols are assigned to a third data stream 2i, then four consecutive symbols are assigned to another third data stream 2i+1, then four consecutive symbols are assigned to the third data stream 2i, and so on, until the distribution of the second data stream is completed. Figure 7(b) shows another implementation of distributing a second data stream in a 1:2 block to obtain two third data streams. Each time, t = 2 RS-FEC-symbol-quartets are distributed. As can be seen from the figure, after the 1:2 block distribution shown in Figure 7(b), two consecutive four-symbols (i.e., eight consecutive symbols) are assigned to a third data stream 2i, and then eight consecutive symbols are assigned to another third data stream 2i+1, and then eight consecutive symbols are assigned to the third data stream 2i, until the distribution of the second data stream is completed. Figure 7(c) shows another implementation of distributing a second data stream in a 1:4 block to obtain four third data streams. Each time, t = 1 RS-FEC symbol-quartet is distributed. As can be seen from the figure, after the 1:4 block distribution shown in Figure 7(c), four consecutive symbols are assigned to a third data stream 4i, then four consecutive symbols are assigned to a third data stream 4i+1, then four consecutive symbols are assigned to a third data stream 4i+2, then four consecutive symbols are assigned to a third data stream 4i+3, and so on, until the distribution of the second data stream is completed.

[0102] 103. Perform convolutional interleaving on each of the m third data streams to obtain m interleaved data streams.

[0103] The following section provides a detailed introduction to convolutional interleaving.

[0104] Specifically, the convolutional interleaver for convolutional interleaving includes r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage unit stores d bits, where d is an integer greater than or equal to 1. Bits from the input data stream of the convolutional interleaver are sequentially input to the r delay lines according to their numbers, with d bits input to each delay line and d bits output from each delay line at a time. In some specific applications, d bits are input to the convolutional interleaver at a time, and these d bits are input to one delay line of the convolutional interleaver. In other specific applications, r × d bits are input to the convolutional interleaver at a time, and these r × d bits are input to the r delay lines of the convolutional interleaver, with the data input to each delay line consisting of d consecutive bits from the r × d bits. The continuous r×d bits in the data stream output by the convolutional interleaver include the d bits output by each delay line.

[0105] It should be understood that the r delay lines each comprise 0, Q, 2Q, ..., (r-1)Q storage units, with each unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) of that delay line to the data stream. It should be understood that when a delay line contains no storage units, the delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0106] Figure 8(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application. As shown in Figure 8(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 8(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application. As shown in Figure 8(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units.

[0107] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0108] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving processing in Figure 8(a) and the convolutional interleaving processing in Figure 8(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 8(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 8(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 8(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 8(a).

[0109] Typically, the number of bits stored in each memory cell is d = a. RS ×10=40. Based on the obtained four-symbol boundaries, the 40 bits stored in each storage unit come from 40 consecutive bits in a third data stream, corresponding to 4 RS symbols, i.e., one RS FEC symbol quartet. The 4 RS symbols come from 4 RS codewords.

[0110] Furthermore, after obtaining m interleaved data streams, data processing including internal code encoding and dual-polarization symbol mapping can be performed on the m interleaved data streams to obtain a single dual-polarization data stream.

[0111] The following uses a third data stream as an example to illustrate the internal code encoding method. Specifically, every K information bits in the third data stream are internally encoded to generate NK check bits, thus obtaining an internal codeword consisting of N bits, where 1 < K < N. In this application, K is considered to be a multiple of 10. Combined with the obtained symbol boundaries, the K information bits in each internal codeword can correspond to K / 10 external code RS symbols.

[0112] In some specific applications, the K information bits in each inner codeword correspond to K / 10 outer code RS symbols, and the corresponding K / 10 outer code RS symbols come from K / 10 outer code RS codewords. This allows the FEC concatenation scheme, which includes RS encoding and inner code encoding, to achieve optimal performance. For example, the inner code encoding uses BCH(126,110), where K=110 information bits in each inner codeword correspond to K / 10=11 outer code symbols, and the corresponding K / 10=11 outer code symbols come from K / 10=11 outer code RS codewords. Another example is the inner code encoding using a linear block code of N=128 and K=120, where K=120 information bits in each inner codeword correspond to K / 10=12 outer code symbols, and the corresponding K / 10=12 outer code symbols come from K / 10=12 different outer code RS codewords. In order to ensure that the K information bits in each internal codeword correspond to K / 10 different external codewords RS, the third data stream also undergoes convolutional interleaving before internal code encoding.

[0113] After the m third data streams are encoded using internal codes, they undergo dual-polarization symbol mapping to obtain a single dual-polarization data stream. This dual-polarization symbol mapping can be dual-polarization quadrature amplitude modulation (DP-QAM). In some specific applications, the dual-polarization symbol mapping can also be DP-16QAM, DP-8QAM, or DP-QPSK symbol mapping, etc.

[0114] In this embodiment, the data processing flow can be divided into two parts. The first data processing may include p:q symbol demultiplexing, alignment identifier locking, and deskewing. The second data processing includes block distribution, convolutional interleaving, internal code encoding, and dual-polarization symbol mapping, and may also include at least one of circular shift, codeword interleaving, and pilot insertion. The pilot insertion is also called framing processing.

[0115] The following examples, using a linear block code with internal code N=126 and K=110 as an example, provide several implementations to illustrate the possible values ​​of p and q.

[0116] Example 1: Consider 1.6TBASE-R transmission, p = 8 and q = 2 × p = 16, m = 2 × q = 32.

[0117] As shown in Figure 9, the eight AUI data streams of 1.6TAUI-8 are PAM4 decoded to obtain p = eight first data streams. This PAM4 decoding is also called PAM4 demodulation or PAM4 decoding. By performing 8:16 symbol demultiplexing and alignment identifier locking on the p = eight first data streams, the four symbol boundaries (also called the four symbol boundaries) of the p = eight first data streams can be obtained, and q = 16 second data streams implementing alignment identifier locking can be obtained. The 8:16 symbol demultiplexing includes p = eight 1:2 symbol demultiplexing operations, as shown in Figure 5(b). Each 1:2 symbol demultiplexing operation uses a round-robin method, distributing 40 bits at a time, to demultiplex the input one first data stream to obtain two output second data streams. These 16 locked second data streams are also called 16 locked data streams.

[0118] The 16 locked data streams are subjected to full deskew or 40-bit deskew to obtain q = 16 second data streams. Based on the obtained four-symbol boundaries, the q = 16 second data streams are distributed in a 1:2 block ratio to obtain m = 32 third data streams. Then, the m third data streams are sequentially subjected to convolutional interleaving, internal code encoding, and cyclic shifting to obtain each fourth data stream. Finally, the m fourth data streams are interleaved and DP-16QAM modulation (also known as symbol mapping) pilot insertion is performed to obtain one DP-16QAM data stream. The 1:2 block distribution can adopt the scheme shown in Figure 7(a) or Figure 7(b); the pilot insertion is also known as framing processing.

[0119] In some implementations, the convolutional interleaver adopts the scheme shown in Figure 8(a), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 7, and each storage unit stores d = 40 bits according to the obtained four-symbol boundary. The 40 bits stored in each storage unit correspond to 4 RS symbols, i.e., one RS FEC four-symbol quartet. In each second data stream after convolutional interleaving, every 12 consecutive RS symbols come from 12 RS codewords. This ensures that any 11 consecutive (adjacent) RS symbols in the output convolutionally interleaved data stream come from 11 RS codewords. Encoding these 11 consecutive RS symbols using BCH(126,110) yields an inner codeword, ensuring that each inner codeword's 110 information bits come from 11 RS codewords. This results in better performance for the concatenated code, and by setting Q=7, the corresponding convolutional interleaving delay is approximately 31ns, resulting in lower system latency and applicability to various transmission scenarios. In some applications, for ease of hardware implementation, Q is required to be even, so Q=8 is used, resulting in a convolutional interleaving delay of approximately 36ns.

[0120] In some other embodiments, the convolutional interleaver adopts the scheme shown in Figure 8(b), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 6, and each storage unit stores d = 40 bits according to the obtained four-symbol boundary. The 40 bits stored in each storage unit correspond to 4 RS symbols, i.e., one RS-FEC four-symbol quartet. In each second data stream after convolutional interleaving, every 12 consecutive RS symbols come from 12 RS codewords. This ensures that any 11 consecutive (adjacent) RS symbols in the convolutionally interleaved data stream output by the convolutional interleaving process come from 11 RS codewords. By performing BCH(126,110) encoding on the 11 consecutive RS symbols in the convolutionally interleaved data stream, an inner codeword is obtained. This allows the 110 information bits of each inner codeword to come from 11 RS codewords, resulting in better performance of the concatenated code. Furthermore, Q=6 can be set, corresponding to a convolutional interleaving delay of approximately 27ns. This also results in a smaller system latency, making it suitable for a wider range of transmission scenarios.

[0121] The cyclic shift adopts the scheme shown in Figure 10, which cyclically shifts the 11RS symbol information data of each BCH(126, 110) internal code, while keeping the 16-bit parity data unchanged. Specifically, the cyclic shift is implemented by right-circularly shifting the i-th RS symbol of the information data in the BCH(126, 110) internal code to the (i+k)%11th symbol, or left-circularly shifting it to the (i+11-Δ)%11th symbol, where 0≤i<11, 0≤k<11, 0≤Δ<11. The scheme shown in Figure 10 can represent a right cyclic shift of k=3 or a left cyclic shift of Δ=8. To improve the burst resistance of the concatenated code, the number of symbols k and Δ cyclically shifted after encoding each third data stream internal code may be different.

[0122] The 1.6T data processing method presented in this embodiment is compatible with the OIF-800LR solution, making it easy to implement in hardware.

[0123] It should be noted that, as shown in Figure 7, PAM4 demodulation of the 8 AUI data streams of 1.6TAUI-8 to obtain p=8 first data streams can be considered as performing 1.6TBASE-R 8:8SM-PMA processing on the 8 AUI data streams of 1.6TAUI-8 to obtain p=8 first data streams. Similarly, the PAM4 decoding, 8:16 symbol demultiplexing, and alignment identifier locking shown in Figure 7 can be considered as performing 1.6TBASE-R 8:16SM-PMA processing to obtain the p=16 locked data streams.

[0124] Example 2: Considering 1.6TBASE-R transmission, the order of internal code encoding and cyclic shift is adjusted based on Example 1, as shown in Figure 11. In this example, the information data of each internal code is first cyclically shifted, and then the cyclically shifted data is encoded using BCH(126,110). As shown in Figure 12, 11 consecutive RS symbols are obtained from the convolutional interleaving data stream output by the convolutional interleaver. These 11 symbols are then cyclically shifted right by k RS symbols, i.e., the i-th RS symbol is cyclically shifted right to the (i+k)%11th symbol; or the 11 symbols are cyclically shifted left by Δ RS symbols, i.e., the i-th RS symbol is cyclically shifted left to the (i+11-Δ)%11th symbol, where 0≤i<11, 0≤k<11, 0≤Δ<11. The scheme shown in Figure 12 can represent a right cyclic shift of k=4 or a left cyclic shift of Δ=7. To improve the burst resistance of concatenated codes, the number of symbols k and Δ cyclically shifted after encoding each third data stream internal code may be different.

[0125] Example 3: Consider 1.6TBASE-R transmission, p = 4 and q = 4 × p = 16, m = 2 × q = 32.

[0126] As shown in Figure 13, the four AUI data streams of 1.6TAUI-4 are processed by 1.6TBASE-R 4:4SM-PMA to obtain p = 4 first data streams. Performing 4:16 symbol demultiplexing and alignment identifier locking on the p = 4 first data streams yields the four symbol boundaries (also called the four symbol boundaries) of the p = 4 first data streams and q = 16 locked second data streams implementing alignment identifier locking. The 4:16 symbol demultiplexing includes p = 4 1:4 symbol demultiplexing operations, as shown in Figure 5(c). Each 1:4 symbol demultiplexing operation uses a round-robin method, distributing 40 bits at a time, to demultiplex the input one first data stream into four output second data streams. These 16 locked second data streams are also called 16 locked data streams.

[0127] The 16 locked data streams are subjected to full deskew or 40-bit deskew to obtain q = 16 second data streams. Based on the obtained four-symbol boundaries, the q = 16 second data streams are first distributed in a 1:2 block ratio to obtain m = 32 third data streams. Then, each of the m third data streams is sequentially subjected to convolutional interleaving, internal code encoding, and cyclic shifting to obtain a fourth data stream. Finally, the m fourth data streams are interleaved and DP-16QAM modulation (also known as symbol mapping) pilot insertion to obtain one DP-16QAM data stream. The block distribution, convolutional interleaving, internal code encoding, and cyclic shifting can adopt the scheme described in Example 1, and will not be repeated here.

[0128] It should be understood that in this embodiment, the data stream output by convolutional interleaving can also be cyclically shifted and then encoded with internal codes to obtain 32 fourth data streams, which can also achieve the same concatenation code performance.

[0129] Example 4: Following the method of Example 1 or Example 3, q ​​= 16 second data streams and the four-symbol boundaries of each second data stream are obtained. Based on the obtained four-symbol boundaries, the q = 16 second data streams are distributed in a 1:4 block ratio to obtain m = 64 third data streams. Then, the m = 64 third data streams are sequentially subjected to convolutional interleaving, internal code encoding, and cyclic shifting to obtain each fourth data stream. Finally, the m = 64 fourth data streams are interleaved and DP-16QAM modulation (also known as symbol mapping) pilot insertion is performed to obtain one DP-16QAM data stream. The 1:4 block distribution can adopt the scheme shown in Figure 7(c); the pilot insertion is also called framing processing.

[0130] In some implementations, the convolutional interleaver adopts the scheme shown in Figure 8(a) or Figure 8(b), where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 4, and each storage unit stores d = 40 bits according to the obtained four-symbol boundary. The 40 bits stored in each storage unit correspond to 4 RS symbols, i.e., one RS FEC four-symbol quartet. In each second data stream after convolutional interleaving, every 12 consecutive RS symbols come from 12 RS codewords. This ensures that any 11 consecutive (adjacent) RS symbols in the convolutionally interleaved data stream output by the convolutional interleaving process come from 11 RS codewords. By performing BCH(126,110) encoding on the 11 consecutive RS symbols in the convolutionally interleaved data stream, an inner codeword is obtained. This allows the 110 information bits of each inner codeword to come from the 11 RS codewords, resulting in better performance of the concatenated code. Furthermore, Q=4 can be set, corresponding to a convolutional interleaving delay of approximately 36ns, which reduces the system latency and makes it suitable for a wider range of transmission scenarios.

[0131] It should be understood that in this embodiment, the data stream output by convolutional interleaving can also be cyclically shifted and then encoded with internal codes to obtain 64 fourth data streams, which can also achieve the same concatenation code performance.

[0132] Figure 14 is a schematic diagram of a data processing device according to an embodiment of this application. As shown in Figure 14, the data processing device includes a first processing unit 1401 and a second processing unit 1402; wherein, the first processing unit 1401 is used to perform the first data processing described in the previous embodiments, such as p:q symbol demultiplexing, alignment identifier locking, and deskipation; the second processing unit 1402 is used to perform the second data processing described in the previous embodiments, such as block distribution, convolutional interleaving, internal code encoding, and dual polarization symbol mapping. In addition, the second data processing may also include at least one of cyclic shifting, codeword interleaving, and pilot insertion. The specific data processing methods have been described in detail in the previous embodiments and will not be repeated here.

[0133] It should be understood that the data processing apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0134] Figure 15 is a schematic diagram of an optical module in an embodiment of this application. As shown in Figure 15, the optical module includes a processor 1501 and an interface 1502. The processor 1501 is used to execute the operations performed by the data processing device in the above embodiments. The interface 1502 can be a transceiver or an input / output interface. The interface 1502 is used to receive signals from other devices and transmit them to the processor 1501 or to send signals from the processor 1501 to other devices. As an example, after the processor 1501 performs the internal code encoding process to obtain an encoded data stream, it sends the encoded data stream through the interface 1502. In this example, the interface 1502 can specifically refer to an electrical interface. As another example, after the processor 1501 performs the internal code encoding process to obtain an encoded data stream, it performs symbol mapping to obtain a symbol stream to be transmitted. The modulator in the optical module performs signal processing such as electro-optic conversion according to the symbol stream to be transmitted to obtain an optical signal, and then sends the optical signal through the interface 1502. In this example, the interface 1502 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 1503, wherein the memory 1503 is used to store program instructions and / or data.

[0135] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0136] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0137] Figure 16 is a schematic diagram of a communication device according to an embodiment of this application. As shown in Figure 16, the communication device includes a host-side device 1601 and an optical module 1602. The host-side device 1601 is used to send data to the optical module 1602, and the optical module 1602 generates an optical signal based on the data sent by the host-side device 1601 and transmits the optical signal through the channel. For example, the host-side device may specifically be a switch, router, server, or optical transport network (OTN) device, etc. This communication device can be a communication device including the host-side device 1601 and the optical module 1602.

[0138] OTN equipment includes line-side equipment and client-side equipment. In some scenarios, client-side equipment may also be referred to as tributary-side equipment. Both client-side and line-side equipment can include a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0139] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0140] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0141] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the data processing method as described in the above embodiments to be implemented.

[0142] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0143] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0144] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0145] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0146] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0147] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0148] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: The p first data streams encoded by Reed-Solomon RS are demultiplexed with p:q symbols, aligned identifier locked and deskewed to obtain q second data streams, where p is an integer greater than or equal to 1, and q is greater than p and an integer multiple of p; The q second data streams are distributed in a 1:n block ratio to obtain m third data streams, where m = n × q, and n is an integer greater than 1; The m third data streams are convolved and interleaved respectively to obtain m interleaved data streams.

2. The method according to claim 1, characterized in that, After obtaining m interleaved data streams, the method further includes: The m interleaved data streams are subjected to data processing including internal code encoding and dual polarization symbol mapping to obtain a single dual polarization data stream.

3. The method according to claim 1 or 2, characterized in that, The step of distributing the q second data streams into 1:n blocks to obtain m third data streams specifically includes: Each second data stream is distributed in a round-robin fashion with h RS symbols as the granularity to obtain n third data streams, for a total of n×q third data streams, where h is an integer greater than or equal to 1, and each RS symbol includes 10 bits.

4. The method according to claim 3, characterized in that, h is a positive integer multiple of 4.

5. The method according to claim 3 or 4, characterized in that, The n is 2, 4, or 8, and the h is 4 or 8.

6. The method according to any one of claims 1-5, characterized in that, q = s × p, where s is 2, 4, or 8.

7. The method according to any one of claims 1-6, characterized in that, The p:q symbol demultiplexing includes p 1:s symbol demultiplexings, wherein each of the p 1:s symbol demultiplexings corresponds one-to-one with a p first data stream.

8. The method according to claim 7, characterized in that, The 1:s symbol demultiplexing adopts a round-robin method of distributing 40 bits each time to demultiplex the corresponding first data stream to obtain s fourth data streams.

9. The method according to claim 8, characterized in that, If at least one of the s fourth data streams fails to achieve alignment identifier locking within the threshold time interval, the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is shifted, and 1:s symbol demultiplexing is performed again to obtain s fourth data streams again. Alignment flag locking is applied to each of the s newly acquired fourth data streams.

10. The method according to claim 9, characterized in that, The granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 1 bit; or The granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0.

11. The method according to any one of claims 1-10, characterized in that, The codeword length of the internal code is 126 bits, of which 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, of which 120 bits are information bits and 8 bits are parity bits.

12. The method according to any one of claims 1-11, characterized in that, The codeword length of the RS is 544 symbols, of which the information length is 514 symbols, and each symbol contains 10 bits.

13. The method according to any one of claims 1-12, characterized in that, The convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

14. The method according to claim 13, characterized in that, Each delay line receives 40 bits as input and outputs 40 bits at a time. After convolution and interleaving, the output data stream contains a continuous r×40 bits, including the 40 bits output by each delay line. The 40 bits stored in the storage unit are 4 RS symbols.

15. The method according to claim 13 or 14, characterized in that, m = 4 × q; the delay line with the largest index among the r delay lines includes 0 memory units, or the delay line with the smallest index among the r delay lines includes 0 memory units; r = 3, Q ≥ 4; Alternatively, m = 2 × q; the delay line with the largest sequence number among the r delay lines includes 0 memory units, r = 3, Q ≥ 7; Alternatively, m = 2 × q; the delay line with the smallest sequence number among the r delay lines includes 0 memory units, r = 3, and Q ≥ 6.

16. The method according to any one of claims 1-15, characterized in that, There is no skew between any two of the q second data streams; or, there is a d skew between any two of the q second data streams. skew The skewness of bits, where d skew It is a multiple of 40.

17. The method according to claim 2, characterized in that, The dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

18. A data processing apparatus, characterized in that, include: First processing unit and second processing unit; The first processing unit is used to perform p:q symbol demultiplexing, alignment identifier locking and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams, where p is an integer greater than or equal to 1, and q is greater than p and is an integer multiple of p; The second processing unit is used to distribute the q second data streams into 1:n blocks to obtain m third data streams, where m = n × q and n is an integer greater than 1; and to perform convolutional interleaving on the m third data streams to obtain m interleaved data streams.

19. The apparatus according to claim 18, characterized in that, The second processing unit is further configured to perform data processing on the m interleaved data streams, including internal code encoding and dual polarization symbol mapping, to obtain a single dual polarization data stream.

20. The apparatus according to claim 18 or 19, characterized in that, The second processing unit is specifically used for: Each second data stream is distributed in a round-robin fashion with h RS symbols as the granularity to obtain n third data streams, for a total of n×q third data streams, where h is an integer greater than or equal to 1, and each RS symbol includes 10 bits.

21. The apparatus according to claim 20, characterized in that, h is a positive integer multiple of 4.

22. The apparatus according to claim 19 or 20, characterized in that, The n is 2, 4, or 8, and the h is 4 or 8.

23. The apparatus according to any one of claims 18-22, characterized in that, q = s × p, where s is 2, 4, or 8.

24. The apparatus according to any one of claims 18-23, characterized in that, The p:q symbol demultiplexing includes p 1:s symbol demultiplexings, wherein each of the p 1:s symbol demultiplexings corresponds one-to-one with a p first data stream.

25. The apparatus according to claim 24, characterized in that, The 1:s symbol demultiplexing adopts a round-robin method of distributing 40 bits each time to demultiplex the corresponding first data stream to obtain s fourth data streams.

26. The apparatus according to claim 25, characterized in that, If at least one of the s fourth data streams fails to achieve alignment identifier locking within the threshold time interval, the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:s symbol demultiplexing, and re-perform 1:s symbol demultiplexing to obtain s fourth data streams again; and perform alignment identifier locking on the s re-obtained fourth data streams respectively.

27. The apparatus according to claim 26, characterized in that, The granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 1 bit; or The granularity of shifting the boundary of the 40 bits distributed in the 1:s symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0.

28. The apparatus according to any one of claims 18-27, characterized in that, The codeword length of the internal code is 126 bits, of which 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, of which 120 bits are information bits and 8 bits are parity bits.

29. The apparatus according to any one of claims 18-28, characterized in that, The codeword length of the RS is 544 symbols, of which the information length is 514 symbols, and each symbol contains 10 bits.

30. The apparatus according to any one of claims 18-29, characterized in that, The convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

31. The apparatus according to claim 30, characterized in that, Each delay line receives 40 bits as input and outputs 40 bits at a time. After convolution and interleaving, the output data stream contains a continuous r×40 bits, including the 40 bits output by each delay line. The 40 bits stored in the storage unit are 4 RS symbols.

32. The apparatus according to claim 30 or 31, characterized in that, m = 4 × q; the delay line with the largest index among the r delay lines includes 0 memory units, or the delay line with the smallest index among the r delay lines includes 0 memory units; r = 3, Q ≥ 4; Alternatively, m = 2 × q; the delay line with the largest sequence number among the r delay lines includes 0 memory units, r = 3, Q ≥ 7; Alternatively, m = 2 × q; the delay line with the smallest sequence number among the r delay lines includes 0 memory units, r = 3, and Q ≥ 6.

33. The apparatus according to any one of claims 18-32, characterized in that, There is no skew between any two of the q second data streams; or, there is a d skew between any two of the q second data streams. skew The skewness of bits, where d skew It is a multiple of 40.

34. The apparatus according to claim 19, characterized in that, The dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

35. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 17.

36. An optical module, characterized in that, The optical module includes a processor and an interface, the processor being used to perform the method as described in any one of claims 1 to 17, and to transmit and receive signals through the interface.

37. A communication device, characterized in that, The transmitting device includes a host-side device and an optical module as described in claim 36, wherein the optical module is connected to the host-side device.

38. A communication system, characterized in that, include: A first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is the communication device as described in claim 37, and the first communication device and the second communication device are connected.

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