Interleaving method and communication apparatus

Abstract

An interleaving method and a communication apparatus. In the method, a first interleaving mode is used to perform row-wise writing and column-wise reading on every [Ki / Qm] bits in an i-th first bit sequence among C acquired first bit sequences, to complete sub-block interleaving. A first matrix determined by performing row-wise writing according to the first interleaving mode comprises ∑i[Ki / Qm] columns; each column of the first matrix comprises Qm bits; the Qm bits are from Qm different first bit sequences among the C first bit sequences, and / or coding-independent first bit sequences; Kirepresents the length of the i-th first bit sequence; and 2Qm represents a modulation order. Therefore, information bits comprised in the C first bit sequences are located at high bits of constellation symbols, and check bits are located at low bits of the constellation symbols, thereby ensuring the performance after bit sequence interleaving.

Description

Interleaving methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202411804477.5, filed on December 9, 2024, entitled "Method and Communication Apparatus for Interleaving", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding, and more specifically, to an interleaving method and a communication apparatus. Background Technology

[0003] Channel bit interleaving enables the transmitted bit sequence to resist burst errors caused by channel fading, thereby improving transmission reliability. In channel bit interleaving, it is necessary to ensure that information bits are located relatively early in the data sequence and parity bits are located relatively late. Alternatively, it can be understood that the information bit sequence must be located in the high-order bits of the constellation symbol, and the parity bit sequence in the low-order bits. This allows the receiving device to process the information bits first and then use the parity bits to detect or correct any potential errors, reducing the error rate of the information bits.

[0004] In some encoding methods, the positional relationship between information bits and parity bits in the data sequence may be changed, resulting in the parity bits after interleaving being located in the high bits of the data sequence, which affects the error rate of information bits. Summary of the Invention

[0005] This application provides an interleaving method and communication device that can avoid the parity bit being in the high bit and ensure the performance of the interleaved bit sequence.

[0006] In the first aspect, an interleaving method is provided, which can be performed by a transmitting device or by a component of the transmitting device (e.g., a chip or circuit), without limitation.

[0007] The method includes: acquiring C first bit sequences, wherein the C first bit sequences are bit sequences to be interleaved, and the information bits in each of the C first bit sequences are placed before the check bits; and performing sub-block interleaving on the C first bit sequences according to a first interleaving method, wherein the first interleaving method is used to interleave each of the i-th first bit sequences in the C first bit sequences. The sub-block interleaving is completed by writing C bits row by row and reading them column by column. The first matrix is ​​a matrix determined by writing C of the first bit sequences row by row. The first matrix includes... Columns, each column in the first matrix includes Q m 1 bit, the Qm The bits include Q from the C first bit sequence. m K different first bit sequences, and / or, encoding unrelated first bit sequences, i This represents the length of the i-th bit sequence of the first bit. Indicates the modulation order. This indicates rounding up to the nearest integer.

[0008] It should be understood that the first interleaving method can be to interleave any one of the C first bit sequences (e.g., the i-th first bit sequence) for each... Bits are written row-wise and read column-wise. Assume the length K of the i-th first bit sequence is... i Cannot be Q m If the result is divisible by Q, then before interleaving, the i-th first bit sequence can be padded with bits so that the length of the padded i-th first bit sequence can be increased by Q. m Integer division. For example, the number of bits filled in the i-th first bit sequence can be expressed as:

[0009] For example, in the C first bit sequences, the information bits of each first bit sequence are placed before the check bits. The C first bit sequences can be regarded as bit sequences concatenated one coupled block at a time, and each first bit sequence can be regarded as a coupled block.

[0010] For example, the method provided in this application can be applied to coupled codes, such as globally coupled low density parity check (GC-LDPC) codes, spatially coupled low density parity check (SC-LDPC) codes, and so on.

[0011] According to the method provided in this application, for each of the C first bit sequences, where the information bits are located before the check bits, a first interleaving method is used for row writing, and column writing completes the sub-block interleaving. Specifically, each column of the first matrix determined by row writing according to the first interleaving method includes Q... m The bits include Q from the C first bit sequence. m Using C different first bit sequences and / or unrelated first bit sequences, the first matrix is ​​read out column by column, thereby ensuring that the information bits included in the C first bit sequences are located in the high bits of the constellation symbol and the parity bits are located in the low bits of the constellation symbol, thus ensuring the performance of the bit sequences after interleaving.

[0012] Meanwhile, the first interleaving method can distribute sudden continuous errors in different encoded bit sequences or in unrelated encoded bit sequences, thereby improving the overall decoding performance.

[0013] In conjunction with the first aspect, in some possible implementations, the sub-block interleaving of the C first bit sequences according to the first interleaving method includes: interleaving each of the C first bit sequences according to Q... m Write rows to obtain the second matrix, which has Q rows. m The number of columns is For the 0th row to the Qth row of the second matrix m The -1 row is then subjected to a first cyclic shift to obtain the first matrix.

[0014] For example, the first cyclic shift can be a leftward shift of each row in the second matrix, or a rightward shift of each row in the second matrix. This application does not limit the direction of the cyclic shift.

[0015] In conjunction with the first aspect, in some possible implementations, the step of performing a first cyclic shift on rows 0 to Qm-1 of the second matrix to obtain the first matrix includes: according to K1 max Given row number q, determine the first value; based on the first value, perform a first cyclic shift on the q-th row of the second matrix to obtain the first matrix, where K1 max Let represent the maximum length of the first bit sequence among the C first bit sequences, where 0 ≤ q ≤ Qm-1, and q is a positive integer.

[0016] For example, row q corresponds to any row in the second matrix.

[0017] For example, based on a first value, perform a first cyclic shift on row q. This first value can be the number of shifts corresponding to the first cyclic shift.

[0018] In conjunction with the first aspect, in some possible implementations, the first value satisfies:

[0019] In conjunction with the first aspect, in some possible implementations, after performing the aforementioned cyclic shift on the x-th bit of the q-th row, the bit at position y of the q-th row satisfies: mod represents the modulo operation.

[0020] In conjunction with the first aspect, in some possible implementations, at least two of the C first bit sequences are encoded as related, and at least two of the C first bit sequences have different lengths.

[0021] In the example, the at least two first bit sequences may be adjacent or not adjacent, and this application does not impose any restrictions.

[0022] For example, when the C first bit sequences belong to the bit sequences in the SC-LDPC code, at least two of the C first bit sequences have different lengths.

[0023] It should be understood that the at least two first bit sequences may be adjacent or non-adjacent, and this application does not impose any restrictions.

[0024] In conjunction with the first aspect, in some possible implementations, the length of each of the C first bit sequences is equal, and at least two of the C first bit sequences are encoded as related. The step of performing a first cyclic shift on rows 0 to Qm-1 of the second matrix to obtain the first matrix includes: according to K... i Given row number q and window length w corresponding to the C first bit sequences, determine the second value; based on the second value, perform the first cyclic shift on the q-th row of the second matrix to obtain the first matrix, where 0≤q≤Qm-1, and q and w are both positive integers.

[0025] Based on the above scheme, the second value is determined based on the window length w corresponding to the C first bit sequences, which enables burst continuous errors to be distributed in different encoded bit sequences or in unrelated encoded bit sequences, thereby improving the overall decoding performance.

[0026] In conjunction with the first aspect, in some possible implementations, the second value satisfies:

[0027] In conjunction with the first aspect, in some possible implementations, the sub-block interleaving of the C first bit sequences according to the first interleaving method includes: for each of the C first bit sequences, the first bit sequence and the second bit sequence are respectively interleaved according to Q... m Write rows to obtain a third matrix, which has Q rows. m The number of columns is The length of the second bit sequence is j, where j is a positive integer; the first cyclic shift is performed on rows 0 to Qm-1 of the third matrix to obtain the first matrix.

[0028] For example, the second bit sequence can be the tail bit sequence. The second bit sequence can be located at any position in the third matrix, and this application does not impose any restrictions.

[0029] In conjunction with the first aspect, in some possible implementations, performing the first cyclic shift on rows 0 to Qm-1 of the third matrix to obtain the first matrix includes: according to K2 max Given row number q and window length w corresponding to the C first bit sequences, determine the third value; based on the third value, perform the first cyclic shift on the q-th row of the third matrix to obtain the first matrix, where K2 max Let w represent the maximum value between the maximum length of the first bit sequence in the C first bit sequences and w, where 0 ≤ q ≤ Qm-1, and q and w are both positive integers.

[0030] Based on the above scheme, the third value is determined based on the window length w corresponding to the C first bit sequences, which enables burst continuous errors to be distributed in different encoded bit sequences or in unrelated encoded bit sequences, thereby improving the overall decoding performance.

[0031] Secondly, a deinterleaving method is provided, which can be performed by the receiving device or by components of the receiving device (such as chips or circuits), without limitation.

[0032] The method includes: taking C fifth-bit sequences, wherein the C fifth-bit sequences are sequences to be deinterleaved, and the information bit corresponding to each of the C fifth-bit sequences is placed before the check bit; and performing de-block interleaving on the C fifth-bit sequences according to a first de-interleaving method, wherein the first de-block interleaving method is used to de-interleave the i-th fifth-bit sequence in the C fifth-bit sequences. The sub-block interleaving is completed by writing each bit column-wise and reading it row-wise. The eighth matrix is ​​a matrix determined by writing C of the fifth bit sequences column-wise. The eighth matrix includes... Each column in the eighth matrix includes Q. m 1 bit, the Q m The bits include those from the same fifth bit sequence in C fifth bit sequences, K i This represents the length of the i-th fifth bit sequence. Indicates the modulation order. This indicates rounding up to the nearest integer.

[0033] It should be understood that the de-intertwining method in the second aspect corresponds to the intertwining method in the first aspect above, and the relevant explanations and technical effects can be found in the description of the first aspect above.

[0034] In conjunction with the second aspect, in some possible implementations, the step of deinterleaving the C fifth bit sequences according to the first deinterleaving method includes: deinterleaving each of the C fifth bit sequences according to Q... m Write the columns to obtain the ninth matrix, which has Q rows. m The number of columns is For the 0th row to the Qth row of the ninth matrix m The -1 row is then subjected to a second cyclic shift to obtain the eighth matrix.

[0035] For example, the second cyclic shift can be a rightward shift of each row in the eighth matrix, or a leftward shift of each row in the eighth matrix. The direction of the second cyclic position can be the same as or different from the direction of the first cyclic shift, which is not limited in this application.

[0036] In conjunction with the second aspect, in some possible implementations, the 0th row to the Qth row of the ninth matrix... m The -1 rows are each subjected to a second cyclic shift to obtain the eighth matrix, including: according to K1 max Given row number q, determine the first value; based on the first value, perform a second cyclic shift on the q-th row of the ninth matrix to obtain the eighth matrix, where K1 max This represents the maximum length of the fifth bit sequence among the C fifth bit sequences, where 0 ≤ q ≤ Q. m -1, where q is a positive integer.

[0037] In conjunction with the second aspect, in some possible implementations, the 0th row to the Qth row of the ninth matrix... m The -1 rows are each subjected to a second cyclic shift to obtain the eighth matrix, including: according to K1 max Given row number q, determine the first value; based on the first value, perform a second cyclic shift on the q-th row of the ninth matrix to obtain the eighth matrix, where K1 max This represents the maximum length of the fifth bit sequence among the C fifth bit sequences, where 0 ≤ q ≤ Q. m -1, where q is a positive integer.

[0038] In conjunction with the second aspect, in some possible implementations, the first value satisfies:

[0039] In conjunction with the second aspect, in some possible implementations, the length of each of the C fifth bit sequences is equal, and at least two of the C fifth bit sequences are encoded as related, wherein the 0th row to the Qth row of the ninth matrix... mThe -1 rows are each subjected to a second cyclic shift to obtain the eighth matrix, including: according to K i The second value is determined by using row number q and window length w corresponding to the C fifth bit sequences; based on the second value, the second cyclic shift is performed on the q-th row of the ninth matrix to obtain the eighth matrix, where 0 ≤ q ≤ Q. m -1, where q and w are both positive integers.

[0040] In conjunction with the second aspect, in some possible implementations, the second value satisfies:

[0041] Thirdly, an interleaving method is provided, which can be performed by the transmitting device or by components of the transmitting device (such as chips or circuits), without limitation.

[0042] The method includes: obtaining a third bit sequence, the third bit sequence being a bit sequence to be interleaved, the third bit sequence comprising C first bit sequences, wherein information bits of the C first bit sequences are located in a first part of the third bit sequence, and check bits of the C first bit sequences are located in a second part of the third bit sequence, the first part preceding the second part; and performing sub-block interleaving on the third bit sequence according to a second interleaving method, wherein the second interleaving method is used to interleave each... The sub-block interleaving is completed by writing bits row by row and reading them column by column. The *a* third matrices are matrices determined by writing the third bit sequence row by row. Each third matrix includes *C* columns, and each column of the third matrix includes *Q*. m 1 bit, the Q m The bits include Q from the C first bit sequence. m K are different first bit sequences, and / or, encoding unrelated first bit sequences, where a is a positive integer and K i This represents the length of the i-th bit sequence of the first bit. Indicates the modulation order. This indicates rounding up to the nearest integer.

[0043] It should be understood that the method provided in this third aspect is similar to the method provided in the first aspect described above. The third bit sequence comprises a first part and a second part, with the first part preceding the second part. The information bits included in the C first bit sequences are located in the first part, and the check bits included in the C first bit sequences are located in the second part. Therefore, the information bits included in the C first bit sequences precede the check bits included in the C first bit sequences.

[0044] According to the method provided in this application, for the third bit sequence, row writing and column reading are performed using a second interleaving method to complete sub-block interleaving. Specifically, a determined third matrices are written row-wise according to the second interleaving method, and each column of each of these a third matrices includes Q. m 1 bit, the Q m The bits come from Q in the third bit sequence. m The third bit sequence is composed of C different first bit sequences, and / or unrelated first bit sequences, thereby ensuring that the information bits of the C first bit sequences included in the third bit sequence are located in the high bits of the constellation symbol and the parity bits are located in the low bits of the constellation symbol, thus ensuring the performance of the bit sequence interleaving.

[0045] In conjunction with the third aspect, in some possible implementations, the sub-block interleaving of the third bit sequence according to the second interleaving method includes: interleaving each of the third bit sequences... Write each bit row by row to obtain a fourth matrix, which has Q rows. m The number of columns is Divide the fourth matrix into C columns to obtain a fifth matrix, each fifth matrix having Q rows. m The number of columns is C; for each of the a fifth matrices, the 0th row to the Qth row... m The -1 rows are each subjected to the first cyclic shift to obtain a third matrices.

[0046] In conjunction with the third aspect, in some possible implementations, the 0th row to the Qth row of each of the a fifth matrices... m The -1 rows are each subjected to a first cyclic shift to obtain a third matrices, including: according to K seg Given row number q, determine the fourth value; based on the fourth value, perform the first cyclic shift on the q-th row of each of the a fifth matrices to obtain a third matrices, where 1 ≤ K. seg <C, 0≤q≤Q m -1, q, and K seg All are positive integers.

[0047] For example, K seg The specific value of K can be predefined or preconfigured. seg It can represent a pre-given reference value for cyclic shifting.

[0048] In conjunction with the third aspect, in some possible implementations, the fourth value satisfies: K seg ×q.

[0049] In conjunction with the third aspect, in some possible implementations, at least two of the C first bit sequences are encoded as related, wherein the 0th row to the Qth row of each of the a fifth matrices... m The -1 rows are each subjected to a first cyclic shift to obtain a third matrices, including: determining a fifth value based on the window length w and row number q corresponding to the C first bit sequences; and performing the first cyclic shift on the q-th row of each of the a fifth matrices based on the fifth value to obtain a third matrices, where 0 ≤ q ≤ Q. m -1, where q and w are both positive integers.

[0050] For example, at least two first bit sequences are encoded as related, and these at least two first bit sequences may be adjacent or not adjacent.

[0051] In conjunction with the third aspect, in some possible implementations, the fifth value satisfies: w × q.

[0052] In conjunction with the third aspect, in some possible implementations, at least two of the C first bit sequences are encoded as related, and the sub-block interleaving of the third bit sequence according to the second interleaving method includes: interleaving each of the C first bit sequences... Write each bit row by row to obtain a fourth matrix, which has Q rows. m The number of columns is Divide the fourth matrix into C columns to obtain a fifth matrix, each fifth matrix having Q rows. m The number of columns is C; arrange the fourth bit sequence according to Qm rows. The columns are added to the *a* fifth matrices to obtain *a* sixth matrices, each sixth matrix having Qm rows and *a* columns. The length of the fourth bit sequence is J, where J is a positive integer, and it is defined for each of the a sixth matrices, from row 0 to row Q. m The -1 rows are each subjected to the first cyclic shift to obtain a third matrices.

[0053] For example, when the fourth bit sequence is added to the fifth matrix, it can be placed at any position in the fifth matrix, and this application does not limit this.

[0054] For example, the fourth bit sequence could be the tail bit sequence.

[0055] In conjunction with the third aspect, in some possible implementations, for each of the a sixth matrices, row 0 to row Q... mThe first cyclic shift is performed on each of the -1 rows to obtain a third matrices, including: determining a sixth value based on the window length w and row number q corresponding to the C first bit sequences; and performing the first cyclic shift on the q-th row of each of the a sixth matrices based on the sixth value to obtain a third matrices, where 0 ≤ q ≤ Q. m -1, where q and w are both positive integers.

[0056] In conjunction with the third aspect, in some possible implementations, the sixth value satisfies: w × q, w ≥ 2.

[0057] Fourthly, a deinterleaving method is provided, which can be performed by the receiving device or by components of the receiving device (such as chips or circuits), without limitation.

[0058] The method includes: obtaining a sixth bit sequence, the sixth bit sequence being a bit sequence to be deinterleaved, the sixth bit sequence comprising C seventh bit sequences, wherein the information bits of the C seventh bit sequences are located in a first part of the sixth bit sequence, and the check bits of the C seventh bit sequences are located in a second part of the sixth bit sequence, the first part preceding the second part; and deinterleaving the sixth bit sequence according to a second deinterleaving method, wherein the second deinterleaving method is used to deinterleave each sub-block of the sixth bit sequence. The bits are written column-wise and read row-wise to complete the interleaving of the decomposed blocks. The *a* tenth matrices are matrices determined by writing the sixth bit sequence column-wise. Each tenth matrix includes *C* columns, and each column of the tenth matrix includes *Q*. m 1 bit, the Q m The bits come from the same seventh bit sequence in C seventh bit sequences, where a is a positive integer, and K... i This represents the length of the i-th seventh bit sequence. Indicates the modulation order. This indicates rounding up to the nearest integer.

[0059] It should be understood that the de-intertwining method in the fourth aspect corresponds to the intertwining method in the third aspect above. For related explanations and technical effects, please refer to the description in the third aspect above.

[0060] In conjunction with the fourth aspect, in one possible implementation, the deinterleaving of the sixth bit sequence according to the second deinterleaving method includes: deinterleaving each sub-block of the sixth bit sequence... Write each bit column-wise to obtain the eleventh matrix, which has Q rows. m The number of columns is Divide the eleventh matrix into C columns to obtain a twelfth matrices, each twelfth matrix having Q rows. m The number of columns is C; for each of the a twelfth matrices, the 0th row to the Qth row... m The -1 rows are each subjected to a second cyclic shift to obtain a tenth matrices.

[0061] In conjunction with the fourth aspect, in one possible implementation, the 0th row to the Qth row of each of the a twelfth matrices... m The -1 rows are each subjected to a second cyclic shift to obtain a tenth matrices, including: according to K seg Given row number q, determine the fourth value; based on the fourth value, perform the second cyclic shift on the q-th row of each of the a twelfth matrices to obtain a tenth matrices, where 1 ≤ K. seg <C, 0≤q≤Q m -1, q, and K seg All are positive integers.

[0062] In conjunction with the fourth aspect, in one possible implementation, the fourth value satisfies: K seg ×q.

[0063] In conjunction with the fourth aspect, in one possible implementation, at least two of the C seventh-bit sequences are encoded as related, wherein the 0th row to the Qth row of each of the a twelfth matrices... m The -1 rows are each subjected to a second cyclic shift to obtain a tenth matrices, including: determining a fifth value based on the window length w and row number q corresponding to the C seventh bit sequences; and performing a second cyclic shift on the q-th row of each of the a twelfth matrices based on the fifth value to obtain a tenth matrices, where 0 ≤ q ≤ Q. m -1, where q and w are both positive integers.

[0064] In conjunction with the fourth aspect, in one possible implementation, the fifth value satisfies: w × q.

[0065] In conjunction with the fourth aspect, in one possible implementation, w is an integer greater than or equal to 2.

[0066] Fifthly, a communication apparatus is provided for performing the methods provided in the first or second aspect. Specifically, the apparatus may include units and / or modules for performing the methods in any of the first or second aspects or any possible implementations of the first or second aspect, such as processing units and / or communication units.

[0067] In one implementation, the device is a transmitting device. When the device is a transmitting device, the communication unit can be a transceiver, or an input / output interface; the processing unit can be at least one processor. Optionally, the transceiver can be a transceiver circuit. Optionally, the input / output interface can be an input / output circuit.

[0068] In another implementation, the device is a chip, chip system, or circuit used in a transmitting device. When the device is a chip, chip system, or circuit used in a transmitting device, the communication unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0069] A sixth aspect provides a communication apparatus for performing the methods provided in the third or fourth aspect. Specifically, the apparatus may include units and / or modules for performing the methods in any of the third or fourth aspects or any possible implementations of the third or fourth aspect, such as processing units and / or communication units.

[0070] In one implementation, the device is a receiving device. When the device is a receiving device, the communication unit can be a transceiver, or an input / output interface; the processing unit can be at least one processor. Optionally, the transceiver can be a transceiver circuit. Optionally, the input / output interface can be an input / output circuit.

[0071] In another implementation, the device is a chip, chip system, or circuit used in a receiving device. When the device is a chip, chip system, or circuit used in a transmitting device, the communication unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0072] A seventh aspect provides a communication device comprising: at least one processor coupled to at least one memory for storing computer programs or instructions, and at least one processor for calling and executing the computer programs or instructions from the at least one memory, such that the communication device performs a method of either the first aspect or the second aspect or any possible implementation thereof.

[0073] In one implementation, the device is a transmitting device.

[0074] In another implementation, the device is a chip, chip system, or circuit used in a transmitting device.

[0075] Eighth aspect, a communication device is provided, the device comprising: at least one processor coupled to at least one memory, the at least one memory for storing computer programs or instructions, and the at least one processor for calling and running the computer programs or instructions from the at least one memory, such that the communication device performs the methods of any of the third or fourth aspects and any possible implementation thereof.

[0076] In one implementation, the device is a receiving device.

[0077] In another implementation, the device is a chip, chip system, or circuit used in a receiving device.

[0078] Ninthly, a processor is provided for executing the methods provided in the foregoing aspects.

[0079] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0080] In a tenth aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any one of the first to fourth aspects or any possible implementation thereof.

[0081] Eleventhly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform any one of the first to fourth aspects and any possible implementation thereof.

[0082] In a twelfth aspect, a chip is provided, the chip including a processor and a communication interface, the processor reading instructions stored in a memory through the communication interface and executing any one of the first to fourth aspects or any possible implementation of the first to fourth aspects.

[0083] Optionally, as one implementation, the chip also includes a memory storing computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to execute any one of the first to fourth aspects or any possible implementation of the first to fourth aspects.

[0084] In a thirteenth aspect, a communication system is provided, which includes the communication devices shown in the sixth and seventh aspects. Attached Figure Description

[0085] Figure 1 is a schematic diagram of the system architecture of the communication system applicable to the technical solution of this application.

[0086] Figure 2 is a schematic diagram of the parity check matrix H of a low density parity check (LDPC).

[0087] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0088] Figure 4 shows the Tanner diagram of the GC-LDPC code.

[0089] Figure 5 is the Tanner diagram of the SC-LDPC code.

[0090] Figure 6 shows the parity check matrix H of an SC-LDPC code. SC A schematic diagram.

[0091] Figure 7 is a schematic diagram of the encoding process of an SC-LDPC code corresponding to a CB.

[0092] Figure 8 is a schematic diagram of an interleaving method.

[0093] Figure 9 is a schematic flowchart of an interleaving method provided in an embodiment of this application.

[0094] Figure 10 is a schematic block diagram of an interleaving method provided in an embodiment of this application.

[0095] Figure 11 is a schematic block diagram of another interleaving method provided in an embodiment of this application.

[0096] Figure 12 is a schematic block diagram of another interleaving method provided in an embodiment of this application.

[0097] Figure 13 is a schematic block diagram of another interlacing method provided in an embodiment of this application.

[0098] Figure 14 is a schematic flowchart of another interleaving method provided in an embodiment of this application.

[0099] Figure 15 is a schematic block diagram of another interleaving method provided in an embodiment of this application.

[0100] Figure 16 is a schematic block diagram of another interleaving method provided in an embodiment of this application.

[0101] Figure 17 is a schematic block diagram of another interleaving method provided in an embodiment of this application.

[0102] Figure 18 is a schematic flowchart of a deinterleaving method provided in an embodiment of this application.

[0103] Figure 19 is a schematic flowchart of another deinterleaving method provided in an embodiment of this application.

[0104] Figure 20 is a schematic block diagram of the communication device 2000 provided in this application.

[0105] Figure 21 is a schematic structural diagram of the communication device 2100 provided in this application. Detailed Implementation

[0106] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0107] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the NR protocol, and related protocols applied to future communication systems; this application does not limit this. Words such as "exemplary," "for example," "exemplarily," and "as (another) example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as an "example" in this application should not be construed as being better or more advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, and "more than one" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when," "under the circumstances," "if," and "if" indicate that the device will take corresponding action under certain objective conditions, not that there is a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0108] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0109] The following describes a communication system to which embodiments of this application can be applied.

[0110] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems or NR systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0111] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0112] For example, Figure 1 shows a schematic diagram of a network architecture to which embodiments of this application may be applied.

[0113] As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application to other communication scenarios is not limited; for example, it can also be applied to sidelink communication.

[0114] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0115] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be a radio controller, relay station, vehicle-mounted equipment, or wearable device in a cloud radio access network (CRAN) scenario. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station may support networks with the same or different access technologies, without limitation.

[0116] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0117] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0118] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (Ultra-Reliable Low-Latency Communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0119] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0120] 1. Low-density parity check (LDPC) code

[0121] LDPC codes are linear block codes, and their parity-check matrix (PCM) is a sparse matrix. The number of zero elements in an LDPC PC ...

[0122] In 1981, Tanner represented the codewords of LDPC graphically, and this type of graph is now called a Tanner graph. Tanner graphs correspond one-to-one with parity-check matrices. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity-check nodes, representing parity-check constraints. Each parity-check node represents a parity-check constraint, which will be explained below with reference to Figures 2 and 3.

[0123] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0124] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0125] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0126] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices, with one vertex serving as both the start and end point, and passing through each node only once. The length of a cycle is defined as the number of connections it contains, and the circumference of the graph, also known as the size of the graph, is defined as the minimum cycle length in the graph. In Figure 3, the circumference is 4, as shown by the bolded connection. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is also corresponding to each codeword bit of the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is also corresponding to the parity bits of the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, then the element (i, j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge.

[0127] Furthermore, in a Tanner graph, a cycle is a closed loop consisting of variable nodes, check nodes, and connecting edges that are connected end to end.

[0128] As mentioned above, LDPC is a linear block code. A linear block code divides the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0129] 2. QC-LDPC code

[0130] Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes. When the code length is long, the parity-check matrix H of an LDPC code can become very large; therefore, H is usually represented in blocks: the complete parity-check matrix H is considered as consisting of multiple Z... c ×Z c The complete parity check matrix H is generated from a submatrix. Specifically, the complete parity check matrix H can be generated from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrices H are such that each submatrix can be represented by a number of cyclically shifted bits, thus greatly reducing the storage space required for the complete parity-check matrix H. Exponential matrix H b The elements in it can also be called QC blocks.

[0131] Based on the exponential matrix H b And the boost value Z c (lifting size) can be used to transform the exponential matrix H b Expanded into a complete parity-check matrix for encoding or decoding. Z c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc. The expansion process involves lifting all elements in the basis matrix to a Z-shape. c ×Z c A square matrix, in which 0 is promoted to Z. c ×Z c The zero matrix is ​​promoted to an identity matrix, and then cyclically shifted based on the shifting value (SV) corresponding to the 1. This cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, 2, and 3, the cyclically shifted matrix after shifting to the right is as follows:

[0132] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0133] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0134] (3) When the translation value is 2, the corresponding cyclically shifted matrix is:

[0135] (4) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0136] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. b The elements in it can also be called QC blocks.

[0137] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0138] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element in the array represents a Z. c A square matrix of order, elements Let represent the cyclic permutation matrix, where i represents the cyclic shift value, and i is an integer. Additionally, let H be the exponent matrix. b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0139] For example, As shown below:

[0140] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0141] It is understandable that the above exponent matrix H... b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0142] It should be noted that the above-mentioned exponential matrix can also be called a base graph (BG). In this application, the base matrix will be used to describe the embodiments of this application. It can be understood that the above-mentioned exponential matrix has corresponding characteristics.

[0143] 3. Globally Coupled (GC) LDPC Code

[0144] For future communication standards, coupled codes have the potential to achieve high-throughput, low-power encoding and decoding. Currently, the two most promising types of coupled codes are globally coupled (GC) LDPC codes and spatially coupled (SC) LDPC codes. In GC-LDPC codes, local codes can be decoded independently, while adjacent local codes in SC-LDPC codes have local coupling relationships. Current 5G standard interleaving schemes only apply to single or local LDPC codes. For different types of coupled codes, we need to design corresponding coupling code interleaving schemes.

[0145] To address the problems of existing LDPC codes, Juane Li et al. proposed GC-LDPC codes in 2016. Their parity check matrix consists of a local matrix and a global matrix. The Tanner diagram of the GC-LDPC code (as shown in Figure 4) utilizes r global parity check nodes to connect c independent LDPC codes in the Tanner diagram {ζ0,ζ1,…,ζ}. c-1 Connect them together, where ζ i ,i=1,…,c-1 represents the Tanner graph corresponding to the local code, with r global check nodes and ζ i The connection represents the Tanner graph corresponding to the global code.

[0146] GC-LDPC codes offer flexibility and excellent structural characteristics. Because their multiple local codes can be decoded independently, they reduce error propagation in environments with low signal-to-noise ratios. Furthermore, the multiple local codes collectively satisfy the constraints of the global check node, effectively resisting sudden errors and improving system performance.

[0147] For the local code ζ in GC-LDPC codes i While algebraic construction can be used, this method struggles to achieve code rate compatibility. To achieve code rate compatibility, the LDPC code defined in the 5G standard is considered, with performance improved through optimized global code construction. The 5G NR standard defines two quasi-cyclic structure basis matrices, BG1 and BG2, for LDPC codes, enabling code rate compatibility. BG1 supports a specific code rate. Adjustable, maximum coded information length is k bmax =8448bit; BG2 supports bitrates Adjustable, maximum coded information length is k bmax =3840 bits. For scenarios with larger code lengths, the existing standard no longer supports them, but GC-LDPC codes can solve this problem by concatenating multiple code blocks.

[0148] The basis matrix B of the GC-LDPC code GC Represented as:

[0149] Among them, the local code base matrix The global code base matrix is ​​of size m0×n0. Its size is r×cn0. Each element in the set satisfies b ij ∈{0,1}. The offset matrix of the GC-LDPC code is represented as... Verification matrix Z is the offset value, H GC With P GC One-to-one correspondence. If b ij =0, then p ij =-1, corresponding to H GC The corresponding position is a zero matrix of size Z×Z; if b ij =1, then p ij ∈{0,1,…,Z-1}, corresponding to H GC The corresponding position is a cyclic permutation matrix of size Z×Z, and the p-th position in the first row of the submatrix is... ij +1 represents non-zero elements.

[0150] 4. SC-LDPC code

[0151] SC-LDPC codes are a class of finite-length LDPC convolutional codes, based on the SC-LDPC code basis matrix B of the original model graph. SC It can be represented as:

[0152] Where L represents the coupling length, m s Indicates the coupling depth. Basis matrix B SC Each column contains m s +1 submatrix, The size of each submatrix is ​​m0×n0. If the basis matrix B SC Satisfy B i (i)=B i (i+1)=…=B i (i+L), i=0,1,….,m s If the code is invariant, it is called a time-invariant SC-LDPC code; otherwise, it is called a time-varying SC-LDPC code. For ease of explanation, the following text will use time-invariant SC-LDPC codes.

[0153] The parity-check matrix B of the SC-LDPC code is used as the basis matrix. SC Expand the matrix and denote the expanded matrix as H. SC Size is [m0(m s The offset matrix corresponding to +L)·Z]×(n0L·Z) is denoted as P SCEach element p in i,j To satisfy p i,j Integers ≥-1. If p i,j =-1, it can be expanded into a zero matrix of size Z×Z; otherwise, it can be expanded into a cyclic shift matrix of size Z×Z identity matrix, where the p-th element in the 0th row of the matrix is... i,j Each element is represented as 1.

[0154] Time-invariant SC-LDPC codes can also be represented by a Tanner diagram, let m s =1, select a subset of variable nodes on the uncoupled Tanner graph at time t and connect them to the next m. s The check nodes on the Tanner graph. Figure 5(a) shows the LDPC code used for coupling, and Figure 5(b) shows the SC-LDPC code generated by copying the Tanner graph shown in Figure 5(a) L times and coupling them.

[0155] When time-invariant SC-LDPC codes undergo L-column truncation, additional check nodes are added and connected to the variable nodes from the previous time step. This results in a loss of code rate. The code rate of SC-LDPC codes is related to the coupling length L and coupling depth m. s Related, when m s When L is constant, increasing L can reduce bitrate loss. When L is infinitely large, bitrate loss is almost non-existent.

[0156] During decoding, the SC-LDPC code can be used to decode the entire parity check matrix H. SC Decoding can also be performed using sliding window decoding. The process of sliding window decoding is illustrated in Figure 6. The window size remains constant, sliding sequentially to the lower right (moving from the solid-line rectangle to the dashed-line rectangle), decoding only the portion within the matrix window each time. Sliding window decoding can reduce complexity and decoding latency.

[0157] The encoding process of a spatially coupled SC-LDPC code corresponding to a CB is shown in Figure 7.

[0158] The SC-LDPC code consists of C blocks and one tail bit block. Each block is considered an LDPC code unit, containing source bits and encoded parity bits. The total input source bit length is K. max The data is divided into different blocks, and encoding is performed sequentially by block. When encoding the first block, only source bit 1 needs to be encoded to obtain parity bit 1. For subsequent blocks, parity bit 2 is obtained by adding source bit 1 and parity bit 1 to source bit 2, parity bit 3 is obtained by adding source bit 2 and parity bit 2 to source bit 3, and so on.

[0159] Additionally, for the last block, the tail parity bit needs to be obtained by adding 4 parity bits to the source bit 4. This ensures the error correction capability of the last block.

[0160] The above encoding method establishes a coupling relationship between adjacent blocks. During decoding, the coupling between blocks can be used to achieve more complete information exchange, thus enabling SC-LDPC codes to achieve superior performance compared to 5G LDPC. Considering the same performance, SC-LDPC codes require fewer iterations than 5G LDPC codes, achieving higher throughput. Furthermore, during decoding, SC-LDPC codes can use a special sliding window decoding structure, which helps reduce decoding storage consumption.

[0161] Current 5G LDPC interleaving involves row-to-row and column-to-column read operations on the encoded bitstream. Here, let the modulation order be Q. m Let the total length of the encoded bitstream be Q. m C int C int For the number of modulation symbols. As shown in Figure 8, for the encoded bitstream fr(0)fr(1)…fr(Q) m C int -1) Perform line writing to obtain Q. m Line, C int The bitstream matrix is ​​column-wise. The interleaved bitstream is read and output column-wise, i.e., fr(0)fr(C) int )fr(2C int )…fr((Q m -1)C int )……fr(C int -1)fr(2C int -1)…fr(Q m C int -1).

[0162] Considering that the coupling code alters the positional relationship between the information bits and the parity bits (as described above in GC-LDPC and SC-LDPC codes), directly using existing interleaving methods would result in the parity bits being located in the high-order bits of the constellation symbol, and burst errors potentially occurring in the same coupling block or coupling blocks that are related to each other, thus affecting the error rate of the information bits. In this embodiment, the high-order bits of the constellation symbol can be simply referred to as the high-order bits, and the low-order bits of the constellation symbol can be simply referred to as the low-order bits.

[0163] Based on the aforementioned problems, this application provides an interleaving method that can be applied to coupled codes, avoids the parity bit being in the high bit, and ensures the performance of the interleaved bit sequence.

[0164] It should be understood that the interleaving method provided in this application can be considered as a channel coding scheme, which can be used in dedicated network equipment or general-purpose equipment, and can be applied to various network equipment (e.g., base station equipment) as described above, as well as various terminal equipment as described above. Specifically, this channel coding scheme is mainly implemented through the channel coding unit in these devices.

[0165] Figure 9 illustrates an interleaving method provided in an embodiment of this application. As shown in Figure 9, the method includes the following steps.

[0166] It is understood that the function shown in Figure 9 can be performed by both the sending and receiving devices. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending or receiving device itself, or to a device that enables the sending or receiving device to perform this function. For ease of description, the following text will use "sending device" and "receiving device" consistently. The sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0167] It is understandable that the method shown in Figure 9 can be applied to coupled codes, such as GC-LDPC codes, SC-LDPC codes, etc.

[0168] 901, The transmitting device acquires C first bit sequences.

[0169] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0170] Here, the C first bit sequences are bit sequences to be interleaved. The C first bit sequences can be bit sequences after channel coding; or, the C first bit sequences can be bit sequences after channel coding and rate matching.

[0171] In this context, each of the C first bit sequences includes information bits preceding the check bits. These C first bit sequences can also be understood as bit sequences cascaded block by block.

[0172] It should be understood that the sequence of C first bits can be represented as: in, This represents the first first bit sequence in a C sequence of first bit sequences, ..., This represents the C-th first bit sequence out of C first bit sequences. Here, C can represent the number of first bit sequences, or it can represent the number of coupling blocks. This represents the j-th bit value in the i-th coupled block.

[0173] 902, The transmitting device performs sub-block interleaving on the C first bit sequences according to the first interleaving method.

[0174] For example, after the transmitting device acquires C first bit sequences, it performs sub-block interleaving on the C first bit sequences according to a first interleaving method. The first interleaving method is used to write each of the C first bit sequences row by row and read them out column by column to complete the sub-block interleaving.

[0175] Taking the i-th first bit sequence out of C first bit sequences as an example, the length of the i-th first bit sequence is K. i , This indicates the modulation order, and the specific value of this modulation order can be predefined or preconfigured. The i-th first bit sequence is calculated according to... Each bit is written row by row. Assume the length of the i-th first bit sequence is K. i =8, modulation order If the value is 16, then the i-th first bit sequence is arranged according to... Each bit is written row by row. Also, assume that the length K of the i-th first bit sequence is... i =7, modulation order If the value is 16, then the i-th first bit sequence is arranged according to... Each bit is written row by row, so the length of the i-th first bit sequence cannot be expressed by Q. m Therefore, before writing row by row, the i-th bit sequence is first padded so that the padded i-th bit sequence can be Q-divisible. m For integers, for example, first fill the i-th first bit sequence with 2 - 7 mod 2 = 1 bit, and the length of the i-th first bit sequence after filling is K. i +1, in relation to K i +1 is written in rows using 2 bits.

[0176] It should be understood that the first matrix is ​​formed by writing each of the C first bit sequences row-wise into a defined matrix, which includes... Column, Q m Rows. Each column contains Q. m 1 bit, the Q m The bits come from the C first bit sequences Q. m A different first bit sequence, and / or, an unrelated first bit sequence.

[0177] In one possible implementation, the transmitting device processes each of the C first bit sequences according to Q... m The rows are written to obtain the second matrix, which includes Q. m OK, The transmitting device transmits each row in the second matrix (e.g., row 0 to row Q). m The first matrix is ​​obtained by performing a first cyclic shift on each row of the second matrix (-1 rows). The shift direction of the first cyclic shift is not limited in this application. For example, the first cyclic shift can be a leftward or rightward shift of each row in the second matrix. In this embodiment, the first cyclic shift is exemplified by a leftward shift, and is not a limitation.

[0178] For example, taking the q-th row of the second matrix as an example, the value of the q-th row after the first cyclic shift is the first value. The transmitting device performs the first cyclic shift on the q-th row of the second matrix according to the first value. Here, the first value is based on K1. max K1 is determined by the row number q. max This represents the maximum length of the first bit sequence in a C-bit sequence, where 0 ≤ q ≤ Q. m -1, where q is a positive integer.

[0179] For example, the first value satisfies

[0180] The following examples, using Example 1 and Example 2, will illustrate the method for determining the first matrix.

[0181] Example 1:

[0182] Suppose C = 9, and the encodings of each of the 9 first bit sequences are uncorrelated, meaning the 9 first bit sequences are independent. For example, these 9 first bit sequences are 9 coupled blocks of a GC-LDPC code, and these 9 coupled blocks are uncorrelated.

[0183] The nine first bit sequences can be represented as: 1111111122222222……99999999, as shown in (1) of Figure 10. In each of the nine first bit sequences, the information bits are located before the check bits. The length of each of the nine first bit sequences is K. i =8. In each of the 9 first bit sequences, the first 4 bits are information bits and the last 4 bits are check bits. Taking the first first bit sequence as an example, in "11111111", the first 4 "1111" are the information bits of the first first bit sequence, and the last 4 "1111" are the check bits of the first first bit sequence.

[0184] The transmitting device according to Q m =4, and write each of the 9 first bit sequences row by row to obtain the second matrix, as shown in (2) of Figure 10. In this matrix, the information bits of each of the 9 first bit sequences are located in the high bits, and the check bits are located in the low bits.

[0185] After determining the second matrix, the transmitting device performs a first cyclic shift on it. The first values ​​corresponding to the first cyclic shift of each row in the second matrix are as follows:

[0186] The row number of the 0th row of the second matrix is ​​0, meaning the first value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the first value corresponding to the 1st row is... The row number of the second row of the second matrix is ​​2, meaning the first value corresponding to this second row is 2. The row number of the third row of the second matrix is ​​3, meaning the first value corresponding to the third row is 3.

[0187] The transmitting device determines the first value corresponding to each row in the second matrix as described above, and performs a cyclic shift on each row of the second matrix to obtain the first matrix, as shown in (3) of Figure 10.

[0188] The transmitting device reads the first matrix shown in (3) of Figure 10 column by column to complete the sub-block interleaving.

[0189] Example 2:

[0190] Suppose C = 9, at least two of the nine first bit sequences are coded correlated, and the window length corresponding to the first bit sequence is 2. For example, the nine first bit sequences are nine coupled blocks of an SC-LDPC code, wherein at least two of the nine coupled blocks are coded correlated, and at least two of the nine coupled blocks have unequal lengths.

[0191] The nine first bit sequences can be represented as: 11111111111122223333333344445555555555556666666667777888899999999. In each of these nine first bit sequences, the information bits precede the check bits, and at least two of the nine first bit sequences have different lengths. The first half of each of these nine first bit sequences consists of information bits, and the second half consists of check bits. Taking the first first bit sequence as an example, in "111111111111", the first six "111111" are the information bits, and the last six "111111" are the check bits.

[0192] The transmitting device according to Q mEach of the nine first bit sequences is written row by row to obtain the second matrix, as shown in (1) of Figure 11. The information bits of each of the nine first bit sequences are located in the high bits, and the check bits are located in the low bits.

[0193] After determining the second matrix, the transmitting device performs a first cyclic shift on the second matrix, where K1 max =12. The first value corresponding to the first cyclic shift of each row in the second matrix is ​​as follows:

[0194] The row number of the 0th row of the second matrix is ​​0, meaning the first value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the first value corresponding to the 1st row is... The row number of the second row of the second matrix is ​​2, meaning the first value corresponding to this second row is 2. The row number of the third row of the second matrix is ​​3, meaning the first value corresponding to the third row is 3.

[0195] The transmitting device determines the first value corresponding to each row in the second matrix as described above, and performs a cyclic shift on each row of the second matrix to obtain the first matrix, as shown in (2) of Figure 11.

[0196] The transmitting device reads the first matrix shown in (2) of Figure 11 column by column to complete the sub-block interleaving.

[0197] It should be understood that, based on Examples 1 and 2 above, after performing the first cyclic shift on the x-th bit of the q-th row, the position of that bit is updated to the y-th bit of the q-th row. This y satisfies... mod represents modulo operation. Taking (2) and (3) in Figure 10 above as examples, after the first cyclic shift of the first bit in the first row, the position of the first bit in the first row is updated to the 17th bit in the first row; taking (1) and (2) in Figure 11 above as examples, after the first cyclic shift of the fifth bit in the second row, the position of the fifth bit in the second row is updated to the 15th bit in the first row.

[0198] In another possible implementation, the transmitting device processes each of the C first bit sequences according to Q... m The rows are written to obtain the second matrix, which includes Q. m OK, The transmitting device transmits each row in the second matrix (e.g., row 0 to row Q). m Perform the first cyclic shift on row -1 to obtain the first matrix.

[0199] For example, if each of the C first bit sequences has the same length, and at least two of the C first bit sequences are encoded as related, taking the q-th row of the second matrix as an example, the value of the first cyclic shift of the q-th row is the second value. The transmitting device performs the first cyclic shift on the q-th row of the second matrix according to the second value. This second value is based on K. i The row number q and the window length w corresponding to the C first bit sequences are determined by K. i Let Q represent the maximum degree of each of the C first bit sequences, where 0 ≤ q ≤ Q. m -1, where q is a positive integer.

[0200] For example, the second value satisfies

[0201] The following example, using Example 3, will provide an exemplary description of the method for determining the first matrix.

[0202] Example 3:

[0203] Assume C = 9, where at least two of the nine first bit sequences are coded correlated, and the window length corresponding to each first bit sequence is 2. For example, these nine first bit sequences can be nine coupled blocks corresponding to an SC-LDPC code, where at least two of these nine coupled blocks are coded correlated, and each of these nine coupled blocks has the same length, i.e., K. i All are equal. The window length w = 2 corresponds to this SC-LDPC code.

[0204] The nine first bit sequences can be represented as: 1111111122222222……99999999, as shown in (1) of Figure 10. In each of the nine first bit sequences, the information bits are located before the check bits, and the length of each of the nine first bit sequences is 8. The first four bits of each of the nine first bit sequences are information bits, and the last four bits are check bits. Taking the first first bit sequence as an example, in "11111111", the first four "1111" are the information bits of the first first bit sequence, and the last four "1111" are the check bits of the first first bit sequence.

[0205] The transmitting device according to Q m =4. Write each of the 9 first bit sequences row by row to obtain the second matrix, as shown in (2) of Figure 10. The information bits of each of the 9 first bit sequences are all in the high bits, and the check bits are all in the low bits.

[0206] After determining the second matrix, the transmitting device performs a first cyclic shift on it. The second values ​​corresponding to the first cyclic shift of each row in the second matrix are as follows:

[0207] The row number of the 0th row of the second matrix is ​​0, meaning the second value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the second value corresponding to the 1st row is... The row number of the second row of the second matrix is ​​2, meaning the second value corresponding to this second row is 2. The row number of the third row of the second matrix is ​​3, meaning the second value corresponding to the third row is 3.

[0208] The transmitting device performs a cyclic shift on each row of the second matrix according to the second value corresponding to each row determined in the above manner to obtain the first matrix, as shown in (4) of Figure 10.

[0209] The transmitting device reads the first matrix column by column to complete the sub-block interleaving.

[0210] In another possible implementation, the transmitting device processes each of the C first bit sequences and the second bit sequence according to Q. m The rows are written to obtain the third matrix, which includes Q. m OK, The column, the second bit sequence has a length of j, where j is a positive integer. The transmitting device then transmits this information to each row of the third matrix (e.g., row 0 to row Q). m Perform the first cyclic shift on row -1 to obtain the first matrix.

[0211] For example, the second bit sequence can be a tail bit sequence (or tail-coupled block, or tail code block). When the transmitting device writes the second bit sequence row by row, the second bit sequence can be located at the end of C first bit sequences, and it can be located at any position in the third matrix (e.g., at the tail). The length of the second bit sequence can be equal to or unequal to the length of the first bit sequence. Assume that the length of the second bit sequence cannot be increased by Q... m For divisibility, bit stuffing is required in the second bit sequence so that the stuffed second bit sequence can be Q-divisible. m Divisible by.

[0212] For example, if each of the C first bit sequences has the same length, and at least two of the C first bit sequences are encoded as related, taking the q-th row of the third matrix as an example, the value of the first cyclic shift of the q-th row is the third value. The transmitting device performs the first cyclic shift on the q-th row of the third matrix according to the third value. This third value is based on K2. maxThe row number q and the window length w corresponding to the C first bit sequences are determined by K2. max Let w represent the maximum value between the maximum value of each of the C first bit sequences and w, where 0 ≤ q ≤ Q. m -1, q, and w are all positive integers.

[0213] For example, the third value satisfies

[0214] The following example, using Example 4, will provide an exemplary description of the method for determining the first matrix.

[0215] Example 4

[0216] Assume C = 9, where at least two of the nine first bit sequences are coded correlated, and the window length corresponding to each first bit sequence is 2. For example, these nine first bit sequences can be nine coupled blocks corresponding to an SC-LDPC code, where at least two of these nine coupled blocks are coded correlated, and each of these nine coupled blocks has the same length, i.e., K. i All are equal. The window length w = 2 corresponds to this SC-LDPC code.

[0217] The nine first bit sequences can be represented as: 1111111122222222……99999999. In each of these nine first bit sequences, the information bits precede the check bits, and each first bit sequence has a length of 8. The first four bits of each of these nine first bit sequences are information bits, and the last four bits are check bits. Taking the first first bit sequence as an example, in "11111111", the first four "1111"s are the information bits, and the last four "1111"s are the check bits. The second bit sequence can be represented as: tttt, j=4. K2 max =8.

[0218] The transmitting device according to Q m =4. Write each of the first bit sequences and second bit sequences in the nine first bit sequences row by row to obtain the third matrix, as shown in (1) of Figure 12. The information bits of each of the nine first bit sequences are located in the high bits and the check bits are located in the low bits. The second bit sequence is located in the last column of the third matrix.

[0219] After determining the third matrix, the transmitting device performs a first cyclic shift on it. The third value corresponding to the first cyclic shift of each row in the third matrix is ​​as follows:

[0220] The row number of the 0th row of the third matrix is ​​0, meaning the second common value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the second common value corresponding to the 1st row is... The row number of the second row of the second matrix is ​​2, meaning the second value corresponding to this second row is 2. The row number of the third row of the second matrix is ​​3, meaning the second value corresponding to the third row is 3.

[0221] The transmitting device performs a cyclic shift on each row of the third matrix according to the third value corresponding to each row determined in the above manner to obtain the first matrix, as shown in (2) of Figure 12.

[0222] The transmitting device reads the first matrix column by column to complete the sub-block interleaving.

[0223] Based on the introduction of Examples 1 to 4 above, the method in Figure 9 above will be described exemplarily below for different modulation orders, C and different lengths corresponding to the first bit sequence.

[0224] Based on the method shown in Figure 9 above, another example of this application embodiment will be given below, as shown in Figure 13.

[0225] Assume Q m =4, C=3, the length of each first bit sequence is equal, and K i =8. The transmitting device writes the three first bit sequences row by row to obtain the second matrix, as shown in (1) of Figure 13. Assuming that the three first bit sequences are uncorrelated, the second matrix is ​​subjected to a first cyclic shift to obtain the first matrix, as shown in (2) of Figure 13. The transmitting device reads the first matrix column by column to complete the sub-block interleaving. Assuming that at least two of the three first bit sequences are correlated and the window length w = 2, the second matrix is ​​subjected to a first cyclic shift to obtain the first matrix, as shown in (3) of Figure 13. The transmitting device reads the first matrix column by column to complete the sub-block interleaving. Assuming that at least two of the three first bit sequences are correlated and the window length w = 2, the transmitting device writes the three first bit sequences and the second bit sequence row by row to obtain the third matrix, as shown in (4) of Figure 13. The transmitting device performs a first cyclic shift on the third matrix to obtain the first matrix, as shown in (5) of Figure 13.

[0226] Based on the description in Figures 9 to 13 above, the interleaving method provided in this application employs a first interleaving method to interleave each of the i-th first bit sequences in the obtained C first bit sequences. Each bit is written row-wise and read column-wise to complete the sub-block interleaving. The first matrix determined by row-wise writing according to the first interleaving method includes... Columns, each column of the first matrix includes Q m bits, Q m The bits include Q from the C first bit sequence. m C different first bit sequences, and / or unrelated first bit sequences, so that the information bits included in the C first bit sequences are in the high bits and the parity bits are in the low bits, thus ensuring the performance of the bit sequences after interleaving.

[0227] Figure 14 illustrates another interleaving method provided in an embodiment of this application. As shown in Figure 14, the method includes the following steps.

[0228] It is understood that the function shown in Figure 14 can be performed by both the sending and receiving devices. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending or receiving device itself, or to a device that enables the sending or receiving device to perform this function. For ease of description, the following text will use "sending device" and "receiving device" consistently. The sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0229] It is understandable that the method shown in Figure 14 can be applied to coupled codes, such as GC-LDPC codes, SC-LDPC codes, etc.

[0230] 1401, The sending device obtains the third bit sequence.

[0231] The third bit sequence is the bit sequence to be interleaved. The third bit sequence includes C first bit sequences, with the information bits of the C first bit sequences located in the first part of the third bit sequence, and the check bits of the C first bit sequences located in the second part of the third bit sequence. The first part of the third bit sequence is located before the second part.

[0232] In this third bit sequence, all information bits of the C first bit sequences are placed before all parity bits. This third bit sequence can also be understood as a sequence of bit-by-bit concatenation of coupled blocks.

[0233] 1402, The transmitting device performs sub-block interleaving on the third bit sequence according to the second interleaving method.

[0234] For example, after acquiring the third bit sequence, the transmitting device performs sub-block interleaving on the third bit sequence according to the second interleaving method. This second interleaving method is used to interleave each... Each bit is written row-wise and read column-wise to complete the sub-block interleaving. Wherein, K i Let represent the length of the i-th first bit sequence (any first bit sequence among the C first bit sequences). This indicates the modulation order. Where K in the C first bit sequences... i They are all equal.

[0235] It should be understood that the length K corresponding to the C first bit sequences i If it cannot be Q m Before writing row-by-row, each of the C first bit sequences needs to be padded with bits so that the length of each first bit sequence in the padded first bit sequence can be multiplied by Q. m Integer. The number of padding bits corresponding to each first bit sequence is: For a specific example, please refer to the description of step 902 in Figure 9 above, which will not be repeated here.

[0236] It should also be understood that the third bit sequence is written row-wise to determine *a* fourth matrices, where *a* is a positive integer. Each of these *a* fourth matrices comprises *C* columns and *Q* columns. m Row. Each column in the fourth matrix includes Q. m 1 bit, the Q m The bits come from Q in the C first bit sequence. m A different first bit sequence, and / or, an unrelated first bit sequence.

[0237] In one possible implementation, the sending device performs a step-by-step analysis on each bit in the third bit sequence. Each bit is written row by row to obtain the fifth matrix, which includes Q. m OK, The transmitting device divides the fifth matrix into C columns, resulting in a sixth matrices. The transmitting device then divides each of these a sixth matrices into each row (e.g., row 0 to row Q). m Perform the first cyclic shift on row -1 to obtain a fourth matrix.

[0238] Example,

[0239] As an example, assume that the encoding of each of the C first bit sequences is unrelated, or that each of the C first bit sequences is encoded independently.

[0240] Taking the q-th row of any one of the *a* sixth matrices as an example, the transmitting device determines the value of the first cyclic shift corresponding to the q-th row as the fourth value. The transmitting device then performs a first cyclic shift on the q-th row of each of the *a* sixth matrices according to this fourth value, resulting in *a* fourth matrices. The fourth value is determined based on K... seg The row number q is determined, and 1 ≤ K seg <C, 0≤q≤Qm -1, q, and K seg All are positive integers. The fourth value after the first circular shift of each row is different. K seg It can be predefined or preconfigured, with K corresponding to each row. seg They can be the same or different; this application makes no limitation on this.

[0241] For example, the fourth value satisfies: K seg ×q.

[0242] The following example, using Example 5, will provide an exemplary description of the method for determining the a fourth matrices.

[0243] Example 5

[0244] Suppose C = 9, and the encodings of each of the 9 first bit sequences are uncorrelated, meaning the 9 first bit sequences are independent. For example, these 9 first bit sequences are 9 coupled blocks of a GC-LDPC code, and these 9 coupled blocks are uncorrelated.

[0245] The third bit sequence comprises nine first bit sequences, each of which has a length of K. i =8. Among them, the information bits of each of the nine first bit sequences are located in the first part of the third bit sequence, and the check bits of each first bit sequence are located in the second part of the third bit sequence. The third bit sequence can be represented as: 123456789123……789123456789123……789, as shown in (1) of Figure 15.

[0246] The transmitting device according to Q m =4. The third bit sequence is written row-wise to obtain the fifth matrix, as shown in (2) of Figure 15. In this third bit sequence, the information bits of the nine first bit sequences are all located in the high-order bits, and the check bits are all in the low-order bits. The fifth matrix has Q rows. m =4, number of columns is

[0247] After determining the fifth matrix, the transmitting device divides the fifth matrix into C columns to obtain a sixth matrix, as shown in (3) of Figure 15.

[0248] The transmitting device performs a first cyclic shift on each of the two sixth matrices. The fourth value corresponding to the first cyclic shift of each row in a sixth matrix can be:

[0249] The row number of the 0th row of the second matrix is ​​0, meaning the fourth value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the fourth value corresponding to the 1st row is K. seg ×q=1×1=1; The row number of the second row of the second matrix is ​​2, meaning the fourth value corresponding to the second row is K. seg ×q=1×2==2; The row number of the third row of the second matrix is ​​3, meaning the fourth value corresponding to the third row is K. seg ×q=1×3=3.

[0250] The transmitting device determines the fourth value corresponding to each row in each sixth matrix according to the above, and performs cyclic shifting on each row of the sixth matrix to obtain a = 2 fourth matrices, as shown in (4) in Figure 15.

[0251] The transmitting device reads each of the two fourth matrices shown in (4) of Figure 15 column by column to complete the sub-block interleaving.

[0252] Example 6

[0253] Suppose C = 9, and the encodings of each of the 9 first bit sequences are uncorrelated, meaning the 9 first bit sequences are independent. For example, these 9 first bit sequences are 9 coupled blocks of a GC-LDPC code, and these 9 coupled blocks are uncorrelated.

[0254] The third bit sequence comprises nine first bit sequences, each of which has a length of K. i =12. Among them, the information bits of each of the nine first bit sequences are located in the first part of the third bit sequence, and the check bits of each first bit sequence are located in the second part of the third bit sequence. The third bit sequence can be represented as: 123456789123……789123456789123……789, as shown in (1) of Figure 16.

[0255] The transmitting device according to Q m =4. The third bit sequence is written row-wise to obtain the fifth matrix, as shown in (2) of Figure 16. In this third bit sequence, the information bits of the nine first bit sequences are all located in the high-order bits, and the check bits are all in the low-order bits. The fifth matrix has Q rows. m =4, number of columns is

[0256] After determining the fifth matrix, the transmitting device divides it into C columns to obtain a sixth matrices. As shown in (3) of Figure 16.

[0257] The transmitting device performs a first cyclic shift on each of the three sixth matrices. The fourth value corresponding to the first cyclic shift of each row in a sixth matrix can be:

[0258] The row number of the 0th row of the second matrix is ​​0, meaning the first value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the fourth value corresponding to the 1st row is K. seg ×q=1×1=1; The row number of the second row of the second matrix is ​​2, meaning the first value corresponding to the second row is K. seg ×q=1×2==2; The row number of the third row of the second matrix is ​​3, meaning the first value corresponding to the third row is K. seg ×q=1×3=3.

[0259] The transmitting device determines the first value corresponding to each row in each sixth matrix according to the above, and performs cyclic shifting on each row of the sixth matrix to obtain a fourth matrix, as shown in (4) of Figure 16.

[0260] The transmitting device reads each of the three fourth matrices (a=3) column by column to complete the sub-block interleaving.

[0261] Example 7

[0262] Assume C = 3, and that the encoding of each of the three first bit sequences is uncorrelated, meaning the three first bit sequences are independent. For example, these three first bit sequences could be three coupled blocks of a GC-LDPC code, and these three coupled blocks are uncorrelated.

[0263] The third bit sequence comprises three first bit sequences, each of which has a length of K. i =12. Among them, the information bits of each of the three first bit sequences are located in the first part of the third bit sequence, and the check bits of each of the first bit sequences are located in the second part of the third bit sequence. The third bit sequence can be represented as: 123123……123123123……123, as shown in (1) of Figure 17.

[0264] The transmitting device according to Q m =4, and the third bit sequence is written row by row to obtain the fifth matrix, as shown in (2) of Figure 17. In this third bit sequence, the information bits of the three first bit sequences are all located in the high bits, and the check bits are all in the low bits. The fifth matrix has Q rows. m =4, number of columns is

[0265] After determining the fifth matrix, the transmitting device divides it into C columns to obtain a sixth matrices. As shown in (3) of Figure 17.

[0266] The transmitting device performs a first cyclic shift on each of the three sixth matrices. The fourth value corresponding to the first cyclic shift of each row in a sixth matrix can be:

[0267] The row number of the 0th row of the second matrix is ​​0, meaning the first value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the fourth value corresponding to the 1st row is K. seg ×q=1×1=1; The row number of the second row of the second matrix is ​​2, meaning the first value corresponding to the second row is K. seg ×q=1×2==2; The row number of the third row of the second matrix is ​​3, meaning the first value corresponding to the third row is K. seg ×q=1×3=3.

[0268] The transmitting device determines the first value corresponding to each row in each sixth matrix based on the above, and performs a cyclic shift on each row of the sixth matrix to obtain a = 3 fourth matrices. As shown in (4) of Figure 17.

[0269] The transmitting device reads each of the a fourth matrices column by column to complete the sub-block interleaving.

[0270] As another example, suppose that the encoding of at least two of the C first bit sequences in the third bit sequence is correlated, or that the encoding of at least two of the C first bit sequences is coupled. Specifically, the positions of the at least two first bit sequences can be adjacent or non-adjacent, which is not limited in this application. The window length corresponding to the C first bit sequences is w.

[0271] Taking the q-th row of any one of the *a* sixth matrices as an example, the transmitting device determines the value of the first cyclic shift corresponding to the q-th row as the fifth value. The transmitting device then performs a first cyclic shift on the q-th row of each of the *a* sixth matrices according to the fifth value, resulting in *a* fourth matrices. The fifth value is determined based on the window length *w* and the row number *q*, where 0 ≤ *q* ≤ *Q*. m -1, where q is a positive integer. The fifth value of the first row after the first circular shift is different.

[0272] For example, the fifth value satisfies: w × q.

[0273] The following section will introduce how to determine the a fourth matrices using Examples 8 to 10.

[0274] Example 8

[0275] Suppose C = 9, and at least two of the nine first bit sequences are coded correlated. For example, these nine first bit sequences are nine coupled blocks of an SC-LDPC code, and at least two of these coupled blocks are correlated.

[0276] The third bit sequence comprises nine first bit sequences, each of which has a length of K. i =8. Among them, the information bits of each of the nine first bit sequences are located in the first part of the third bit sequence, and the check bits of each first bit sequence are located in the second part of the third bit sequence. The third bit sequence can be represented as: 123456789123……789123456789123……789.

[0277] The transmitting device according to Q m =4, and the third bit sequence is written row by row to obtain the fifth matrix, as shown in (2) of Figure 15. In this third bit sequence, the information bits of the 9 first bit sequences are all located in the high bits, and the check bits are all in the low bits. The fifth matrix has Q rows. m =4, number of columns is

[0278] After determining the fifth matrix, the transmitting device divides it into C columns to obtain a sixth matrices. As shown in (3) of Figure 15.

[0279] The transmitting device performs a first cyclic shift on each of the two sixth matrices. The fifth value corresponding to the first cyclic shift on each row of each sixth matrix can be:

[0280] The row number of the 0th row of the second matrix is ​​0, meaning the fifth value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the fifth value corresponding to the 1st row is w×q=2×1=1; the row number of the 2nd row of the second matrix is ​​2, meaning the fifth value corresponding to the 2nd row is w×q=2×2==4; the row number of the 3rd row of the second matrix is ​​3, meaning the fifth value corresponding to the 3rd row is w×q=2×3=6.

[0281] The transmitting device determines the fifth value corresponding to each row in each sixth matrix based on the above, and performs a cyclic shift on each row of the sixth matrix to obtain a = 2 fourth matrices. As shown in (5) of Figure 15.

[0282] The transmitting device reads each of the a fourth matrices column by column to complete the sub-block interleaving.

[0283] Example 9

[0284] Assume C = 9, and at least two of the nine first-bit sequences are coded correlated. For example, these nine first-bit sequences are nine coupled blocks of an SC-LDPC code, and at least two of these coupled blocks are correlated. We will use an example with a window length w = 2 corresponding to the first-bit sequence.

[0285] The third bit sequence comprises nine first bit sequences, each of which has a length of K. i =12. Among them, the information bits of each of the 9 first bit sequences are located in the first part of the third bit sequence, and the check bits of each first bit sequence are located in the second part of the third bit sequence. The third bit sequence can be represented as: 123456789123……789123456789123……789.

[0286] The transmitting device according to Q m =4. Write the third bit sequence row by row to obtain the fifth matrix. In this third bit sequence, the 9 information bits of the first bit sequence are all in the high-order bits, and the check bits are all in the low-order bits. The fifth matrix has Q rows. m =4, number of columns is As shown in (2) of Figure 16.

[0287] After determining the fifth matrix, the transmitting device divides it into C columns to obtain a sixth matrices. As shown in (3) of Figure 16.

[0288] The transmitting device performs a first cyclic shift on each of the three sixth matrices. The fifth value corresponding to the first cyclic shift of each row in a sixth matrix can be:

[0289] The row number of the 0th row of the second matrix is ​​0, meaning the fifth value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the fifth value corresponding to the 1st row is w×q=2×1=2; the row number of the 2nd row of the second matrix is ​​2, meaning the fifth value corresponding to the 2nd row is w×q=2×2==4; the row number of the 3rd row of the second matrix is ​​3, meaning the fifth value corresponding to the 3rd row is w×q=2×3=6.

[0290] The transmitting device determines the fifth value corresponding to each row in each sixth matrix based on the above, and performs a cyclic shift on each row of each sixth matrix to obtain a fourth matrix. As shown in (5) of Figure 16.

[0291] The transmitting device reads each of the a fourth matrices column by column to complete the sub-block interleaving.

[0292] Example 10

[0293] Assume C = 3, and at least two of the three first bit sequences are coded correlated. For example, these three first bit sequences are three coupled blocks of an SC-LDPC code, and at least two of these coupled blocks are correlated. We will use a window length w = 2 corresponding to the first bit sequence as an example.

[0294] The third bit sequence comprises three first bit sequences, each of which has a length of K. i =12. The information bits of each of the three first bit sequences are located in the first part of the third bit sequence, and the check bits of each first bit sequence are located in the second part of the third bit sequence. The third bit sequence can be represented as: 123123……123123123……123.

[0295] The transmitting device according to Q m =4. Write the third bit sequence row by row to obtain the fifth matrix. In this third bit sequence, the information bits of the three first bit sequences are all in the high-order bits, and the check bits are all in the low-order bits. The fifth matrix has Q rows. m =4, number of columns is As shown in (2) of Figure 17.

[0296] After determining the fifth matrix, the transmitting device divides it into C columns to obtain a sixth matrices. As shown in (3) of Figure 17.

[0297] The transmitting device performs a first cyclic shift on each of the three sixth matrices. The fifth value corresponding to the first cyclic shift of each row in a sixth matrix can be:

[0298] The row number of the 0th row of the second matrix is ​​0, meaning the fifth value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the fifth value corresponding to the 1st row is w×q=2×1=2; the row number of the 2nd row of the second matrix is ​​2, meaning the fifth value corresponding to the 2nd row is w×q=2×2==4; the row number of the 3rd row of the second matrix is ​​3, meaning the fifth value corresponding to the 3rd row is w×q=2×3=6.

[0299] The transmitting device determines the fifth value corresponding to each row in each sixth matrix based on the above, and performs a cyclic shift on each row of the sixth matrix to obtain a fourth matrix. As shown in (5) of Figure 17.

[0300] The transmitting device reads each of the a fourth matrices column by column to complete the sub-block interleaving.

[0301] For example, if the encoding of at least two of the C first bit sequences in the third bit sequence is related, the transmitting device can arrange the fourth bit sequence according to Qm rows. Each column is added to one of the *a* sixth matrices, resulting in *a* seventh matrices. Each of these *a* seventh matrices has *Qm* rows and *n* columns. The length of the fourth bit sequence is J, where J is a positive integer.

[0302] For example, the fourth bit sequence can be a tail bit sequence (or tail-coupled block, or tail code block). When the transmitting device writes the fourth bit sequence row by row, the fourth bit sequence can be located at the end of the third bit sequence, or it can be located at any position (e.g., the tail) in each seventh matrix. The length of the fourth bit sequence can be equal to or unequal to the length of the first bit sequence. Assume that the length of the fourth bit sequence cannot be Q... m For divisibility, the fourth bit sequence needs to be padded so that the padded fourth bit sequence can be Q-divisible. m Divisible by.

[0303] Taking the q-th row of one of the a seventh matrices as an example, the value obtained by the first cyclic shift of the q-th row is the sixth value. The transmitting device performs the first cyclic shift on the q-th row of the seventh matrix according to the sixth value. This sixth value is determined based on the window length w and row number q corresponding to the first bit sequence.

[0304] For example, the sixth value satisfies q × w. Where w ≥ 2.

[0305] Referring to the examples shown in Figures 15 to 17 above, assuming the length of the fourth bit sequence is 4, the transmitting device adds a column to each of the a sixth matrices, where the column includes 4 bits "tttt", resulting in a seventh matrices. Assume that the "tttt" column is located in the last column of the seventh matrix, meaning the seventh matrix is ​​the sixth matrix plus a column "tttt". See (6) in Figure 15, (6) in Figure 16, and (6) in Figure 17.

[0306] The transmitting device performs a first cyclic shift on each of the *a* seventh matrices. The sixth value corresponding to the first cyclic shift of each row in a seventh matrix can be:

[0307] The row number of the 0th row of the second matrix is ​​0, meaning the sixth value corresponding to the 0th row is 0; the row number of the 1st row of the second matrix is ​​1, meaning the sixth value corresponding to the 1st row is w×q=2×1=2; the row number of the 2nd row of the second matrix is ​​2, meaning the sixth value corresponding to the 2nd row is w×q=2×2==4; the row number of the 3rd row of the second matrix is ​​3, meaning the sixth value corresponding to the 3rd row is w×q=2×3=6.

[0308] The transmitting device determines the sixth value corresponding to each row in each seventh matrix based on the above, and performs a cyclic shift on each row in the seventh matrix to obtain a fourth matrix. As shown in (7) in Figure 15, (7) in Figure 16, and (7) in Figure 17.

[0309] The transmitting device reads each of the four fourth matrices described above column by column to complete the sub-block interleaving.

[0310] Based on the description in Figures 14-17 above, the interleaving method provided in this application completes sub-block interleaving by writing the obtained third bit sequence row by row and reading it column by column using a second interleaving method. Specifically, a determined third matrices are written row by row according to the second interleaving method, and each column of each of these a third matrices includes Q. m 1 bit, the Q m The bits come from Q in the third bit sequence. m The third bit sequence is composed of C different first bit sequences, and / or unrelated first bit sequences, thereby ensuring that the information bits of the C first bit sequences included in the third bit sequence are located in the high bits of the constellation symbol and the parity bits are located in the low bits of the constellation symbol, thus ensuring the performance of the bit sequence interleaving.

[0311] Figure 18 is a schematic diagram of a deinterleaving method provided in an embodiment of this application. As shown in Figure 18, the method may include the following steps.

[0312] It should be understood that Figure 18 corresponds to the interleaving method shown in Figure 9 above, and those skilled in the art can reasonably derive the corresponding deinterleaving method based on the interleaving method described in Figure 9 above.

[0313] 1801, The receiving device acquires C fifth bit sequences.

[0314] Among them, the C fifth-bit sequences are sequences to be deinterleaved, or they can be understood as soft bit sequences. The information bit corresponding to each of the C fifth-bit sequences comes before the check bit.

[0315] It should be understood that the process by which the receiving device acquires the sequence of C fifth bits can be found in the description of existing schemes, and will not be repeated here.

[0316] 1802, The receiving device performs de-block interleaving on the C fifth bit sequences according to the first de-interleaving method.

[0317] The first de-interleaving method is used to de-interleave the i-th fifth bit sequence in C fifth bit sequences. Each bit is written column-wise and read row-wise to complete the sub-block interleaving. The eighth matrix is ​​a matrix determined by writing C fifth bit sequences column-wise. The eighth matrix includes... Columns, each column in the eighth matrix includes Q m bits, Q m The bits include the same fifth bit sequence from C fifth bit sequences, K i This represents the length of the i-th fifth bit sequence. Indicates the modulation order.

[0318] In one possible implementation, the receiving device processes each of the C fifth-bit sequences according to Q... m Write the columns to obtain the ninth matrix, which has Q rows. m The number of columns is The receiving device uses row 0 to row Q of the ninth matrix. m The -1 row is then subjected to a second cyclic shift to obtain the eighth matrix.

[0319] The second cyclic shift can be the opposite direction to the first cyclic shift in Figure 9. For example, if the first cyclic shift is to the left, the second cyclic shift is to the right; or if the first cyclic shift is to the right, the second cyclic shift is to the left.

[0320] As an example, the receiving device is based on K1 max The first value is determined by the row number q; the receiving device performs a second cyclic shift on the q-th row of the ninth matrix based on the first value to obtain the eighth matrix, where K1 max Let q represent the maximum length of the fifth bit sequence in C fifth bit sequences, where 0 ≤ q ≤ Q. m -1, where q is a positive integer.

[0321] For example, the first value satisfies

[0322] As another example, if the length of each of the C fifth bit sequences is equal, and at least two of the C fifth bit sequences are co-coded, the receiving device determines the order based on K. i The second value is determined by the row number q and the window length w corresponding to the C fifth bit sequences. Based on this second value, the receiving device performs a second cyclic shift on the q-th row of the ninth matrix to obtain the eighth matrix, where 0 ≤ q ≤ Q. m -1, where q and w are both positive integers.

[0323] For example, the second value satisfies

[0324] It should be understood that the detailed example of deinterleaving corresponding to Figure 18 above corresponds to the specific example in Figure 9 above, and will not be repeated here.

[0325] Figure 19 is a schematic diagram of another deinterleaving method provided in an embodiment of this application. As shown in Figure 19, the method may include the following steps.

[0326] It should be understood that Figure 19 corresponds to the interleaving method shown in Figure 14 above, and those skilled in the art can reasonably derive the corresponding deinterleaving method based on the interleaving method described in Figure 14 above.

[0327] It should also be understood that for a detailed explanation of some of the parameters in Figure 19, please refer to the description in Figure 14 above.

[0328] 1901, the receiving device acquires the sixth bit sequence.

[0329] The sixth bit sequence is the bit sequence to be deinterleaved. The sixth bit sequence includes C seventh bit sequences. The information bits of the C seventh bit sequences are located in the first part of the sixth bit sequence, and the check bits of the C seventh bit sequences are located in the second part of the sixth bit sequence. The first part is located before the second part.

[0330] It should be understood that the process by which the receiving device obtains the sixth bit sequence can be found in the description of existing schemes, and will not be repeated here.

[0331] 1902, The receiving device performs sub-block interleaving on the sixth bit sequence according to the second deinterleaving method.

[0332] The second deinterleaving method is used to deinterleave each bit in the sixth bit sequence. Each bit is written column-wise and read row-wise to complete the deinterleaving of sub-blocks. The 'a' tenth matrices are matrices defined by writing the sixth bit sequence column-wise. Each tenth matrix contains C columns, and each column of the tenth matrix contains Q. m bits, Q m The bits come from the same seventh bit sequence among C seventh bit sequences, where a is a positive integer, and K... i This represents the length of the i-th seventh bit sequence. Indicates the modulation order. This indicates rounding up to the nearest integer.

[0333] In one possible implementation, the receiving device performs a step-by-step analysis on each bit in the sixth bit sequence. Write each bit column-wise to obtain the eleventh matrix, which has Q rows. m The number of columns is The receiving device divides the eleventh matrix into C columns to obtain a twelfth matrices, each twelfth matrix having Q rows. m The number of columns is C; the receiving device analyzes the 0th row to the Qth row of each of the a twelfth matrices. m The -1 rows are then subjected to a second cyclic shift to obtain a tenth matrices.

[0334] As an example, the receiving device is based on K seg Given row number q, determine the fourth value; based on the fourth value, the receiving device performs a second cyclic shift on the q-th row of each of the a twelfth matrices to obtain a tenth matrices, where 1 ≤ K. seg <C, 0≤q≤Q m -1, q, and K seg All are positive integers.

[0335] For example, the fourth value satisfies: K seg ×q

[0336] As another example, the receiving device determines the fifth value based on the window length w and row number q corresponding to the C seventh bit sequences; based on the fifth value, the receiving device performs a second cyclic shift on the q-th row of each of the a twelfth matrices to obtain a tenth matrices, where 0 ≤ q ≤ Q. m -1, where q and w are both positive integers.

[0337] For example, the fifth value satisfies w × q, where w can be an integer greater than or equal to 2.

[0338] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0339] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0340] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0341] Corresponding to the methods described in the above embodiments, this application also provides corresponding apparatuses, which include modules for executing the methods described above. These modules can be software, hardware, or a combination of both. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0342] Figure 20 is a schematic block diagram of a communication device 2000 provided in an embodiment of this application. As shown in Figure 20, the device 2000 may include a communication unit 2010 and a processing unit 2020. The communication unit 2010 can communicate with the outside world, and the processing unit 2020 is used for data processing. The communication unit 2010 may also be referred to as a communication interface or a transceiver unit.

[0343] In one possible design, the device 2000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 2020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 2010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0344] In another possible design, the device 2000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 2010 is used to perform reception-related operations of the receiving device in the above method embodiments, and the processing unit 2020 is used to perform processing-related operations of the receiving device in the above method embodiments.

[0345] It should be understood that the device 2000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, combined logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 2000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 2000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0346] The apparatus 2000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 2000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0347] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In the embodiments of this application, the device in FIG20 can be the receiving end device or transmitting end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0348] Figure 21 is a schematic block diagram of a communication device 2100 provided in an embodiment of this application. The device 2100 includes a processor 2110 and a transceiver 2120. The processor 2110 and the transceiver 2120 communicate with each other through an internal connection path. The processor 2110 is used to execute instructions to control the transceiver 2120 to send and / or receive signals.

[0349] Optionally, the device 2100 may further include a memory 2130, which communicates with the processor 2110 and the transceiver 2120 via an internal connection path. The memory 2130 stores instructions, and the processor 2110 can execute the instructions stored in the memory 2130. In one possible implementation, the device 2100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 2100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0350] It should be understood that the device 2100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 2120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 2100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments. Optionally, the memory 2130 may include read-only memory and random access memory, and provide instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store device type information. The processor 2110 can be used to execute the instructions stored in the memory, and when the processor 2110 executes the instructions stored in the memory, the processor 2110 is used to execute the various steps and / or processes of the above method embodiments corresponding to the transmitting or receiving device.

[0351] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0352] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0353] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0354] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0355] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0356] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0357] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0358] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0359] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0360] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0361] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0362] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0363] It should be understood that the term "embodiment" used throughout this specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout this specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0364] It should also be understood that in this application, “when…”, “if” and “if” all refer to the network element making a corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0365] It should also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0366] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of interlacing, characterized in that, include: Obtain C first bit sequences, which are bit sequences to be interleaved, with the information bit in each of the C first bit sequences preceding the check bit; The C first bit sequences are interleaved using a first interleaving method, wherein the first interleaving method is used to interleave each of the i-th first bit sequences in the C first bit sequences into sub-blocks. The sub-block interleaving is completed by writing C bits row by row and reading them column by column. The first matrix is ​​a matrix determined by writing C of the first bit sequences row by row. The first matrix includes... Columns, each column in the first matrix includes Q m 1 bit, the Q m The bits include Q from the C first bit sequence. m K different first bit sequences, and / or, encoding unrelated first bit sequences, i This represents the length of the i-th bit sequence of the first bit. Indicates the modulation order. This indicates rounding up to the nearest integer.

2. The method according to claim 1, characterized in that, The step of performing sub-block interleaving on the C bits of the first bit sequence according to the first interleaving method includes: For each of the C first bit sequences, according to Q m Write rows to obtain the second matrix, which has Q rows. m The number of columns is For the 0th row to the Qth row of the second matrix m The -1 row is then subjected to a first cyclic shift to obtain the first matrix.

3. The method according to claim 2, characterized in that, The step of performing a first cyclic shift on rows 0 to Qm-1 of the second matrix to obtain the first matrix includes: According to K1 max And the row number q, determine the first value; Based on the first value, perform a first cyclic shift on the q-th row of the second matrix to obtain the first matrix. Among them, K1 max Let represent the maximum length of the first bit sequence among the C first bit sequences, where 0 ≤ q ≤ Qm-1, and q is a positive integer.

4. The method according to claim 3, characterized in that, The first value satisfies:

5. The method according to claim 2, characterized in that, Each of the C first bit sequences has the same length, and at least two of the C first bit sequences are coded as related. The step of performing a first cyclic shift on rows 0 to Qm-1 of the second matrix to obtain the first matrix includes: According to K i The second value is determined by the row number q and the window length w corresponding to the C first bit sequences; Based on the second value, the q-th row of the second matrix is ​​subjected to the first cyclic shift to obtain the first matrix. Where 0≤q≤Qm-1, and q and w are both positive integers.

6. The method according to claim 5, characterized in that, The second value satisfies:

7. A method of interlacing, characterized in that, include: Obtain a third bit sequence, which is a bit sequence to be interleaved. The third bit sequence includes C first bit sequences, where the information bits of the C first bit sequences are located in the first part of the third bit sequence, and the check bits of the C first bit sequences are located in the second part of the third bit sequence, with the first part preceding the second part. The third bit sequence is sub-block interleaved according to the second interleaving method, wherein the second interleaving method is used to interleave each of the third bit sequence... The sub-block interleaving is completed by writing bits row by row and reading them column by column. The a fourth matrix is ​​a matrix determined by writing the third bit sequence row by row. The fourth matrix includes C columns, and each column of the fourth matrix includes Q. m 1 bit, the Q m The bits include Qm distinct first bit sequences from C first bit sequences, and / or, encoding unrelated first bit sequences, where a is a positive integer, and K i This represents the length of the i-th bit sequence of the first bit. Indicates the modulation order. This indicates rounding up to the nearest integer.

8. The method according to claim 7, characterized in that, The sub-block interleaving of the third bit sequence according to the second interleaving method includes: For each of the third bit sequences Each bit is written row by row to obtain the fifth matrix, which has Q rows. m The number of columns is Divide the fifth matrix into C columns to obtain a sixth matrix, each sixth matrix having Q rows. m The number of columns is C; For each of the a sixth matrices, row 0 to row Q... m The -1 rows are each subjected to the first cyclic shift to obtain a fourth matrix.

9. The method according to claim 8, characterized in that, The 0th row to the Qth row of each of the a sixth matrices m The -1 rows are each subjected to a first cyclic shift to obtain a fourth matrix, including: According to K seg And the row number q, determine the fourth value; Based on the fourth value, the first cyclic shift is performed on the q-th row of each of the a sixth matrices to obtain a fourth matrices. Where 1≤K seg <C, 0≤q≤Q m -1, q, and K seg All are positive integers.

10. The method according to claim 9, characterized in that, The fourth value satisfies: K seg ×q.

11. The method according to claim 8, characterized in that, At least two of the C first bit sequences are encoded as related. The 0th row to the Qth row of each of the a sixth matrices m The -1 rows are each subjected to a first cyclic shift to obtain a fourth matrix, including: The fifth value is determined based on the window length w and row number q corresponding to the C first bit sequences; Based on the fifth value, the first cyclic shift is performed on the q-th row of each of the a sixth matrices to obtain a fourth matrices. Where 0≤q≤Q m -1, where q and w are both positive integers.

12. The method according to claim 11, characterized in that, The fifth value satisfies: w × q.

13. A method for de-intertwining, characterized in that, include: Obtain C fifth bit sequences, where the C fifth bit sequences are sequences to be deinterleaved, and the information bit corresponding to each of the C fifth bit sequences precedes the check bit; The C fifth bit sequences are de-interleaved according to the first de-interleaving method, wherein the first de-interleaving method is used to de-interleave the i-th fifth bit sequence among the C fifth bit sequences. The sub-block interleaving is completed by writing each bit column-wise and reading it row-wise. The eighth matrix is ​​a matrix determined by writing C of the fifth bit sequences column-wise. The eighth matrix includes... Each column in the eighth matrix includes Q. m 1 bit, the Q m The bits include those from the same fifth bit sequence in C fifth bit sequences, K i This represents the length of the i-th fifth bit sequence. Indicates the modulation order. This indicates rounding up to the nearest integer.

14. The method according to claim 13, characterized in that, The step of deinterleaving the C fifth bit sequences according to the first deinterleaving method includes: For each of the C fifth bit sequences, according to Q m Write the columns to obtain the ninth matrix, which has Q rows. m The number of columns is For the 0th row to the Qth row of the ninth matrix m The -1 row is then subjected to a second cyclic shift to obtain the eighth matrix.

15. The method according to claim 14, characterized in that, The 0th row to the Qth row of the ninth matrix m The -1 rows are each subjected to a second cyclic shift to obtain the eighth matrix, which includes: According to K1 max And the row number q, determine the first value; Based on the first value, a second cyclic shift is performed on the q-th row of the ninth matrix to obtain the eighth matrix. Among them, K1 max This represents the maximum length of the fifth bit sequence among the C fifth bit sequences, where 0 ≤ q ≤ Q. m -1, where q is a positive integer.

16. The method according to claim 14, characterized in that, Each of the C fifth-bit sequences has the same length, and at least two of the C fifth-bit sequences are coded as related. The 0th row to the Qth row of the ninth matrix m The -1 rows are each subjected to a second cyclic shift to obtain the eighth matrix, which includes: According to K i The second value is determined by the row number q and the window length w corresponding to the C fifth bit sequences; Based on the second value, the q-th row of the ninth matrix is ​​subjected to the second cyclic shift to obtain the eighth matrix. Where 0≤q≤Q m -1, where q and w are both positive integers.

17. A method for uninterrupting interlacing, characterized in that, include: Obtain the sixth bit sequence, which is a bit sequence to be deinterleaved. The sixth bit sequence includes C seventh bit sequences, where the information bits of the C seventh bit sequences are located in the first part of the sixth bit sequence, and the check bits of the C seventh bit sequences are located in the second part of the sixth bit sequence. The first part is located before the second part. The sixth bit sequence is de-interleaved according to the second de-interleaving method, wherein the second de-interleaving method is used to de-interleave each sub-block of the sixth bit sequence. The bits are written column-wise and read row-wise to complete the interleaving of the decomposed blocks. The *a* tenth matrices are matrices determined by writing the sixth bit sequence column-wise. Each tenth matrix includes *C* columns, and each column of the tenth matrix includes *Q*. m 1 bit, the Q m The bits come from the same seventh bit sequence in C seventh bit sequences, where a is a positive integer, and K... i This represents the length of the i-th seventh bit sequence. Indicates the modulation order. This indicates rounding up to the nearest integer.

18. The method according to claim 17, characterized in that, The step of deinterleaving the sixth bit sequence according to the second deinterleaving method includes: For each of the sixth bit sequences Write each bit column-wise to obtain the eleventh matrix, which has Q rows. m The number of columns is Divide the eleventh matrix into C columns to obtain a twelfth matrices, each twelfth matrix having Q rows. m The number of columns is C; For each of the a twelfth matrices, row 0 to row Q... m The -1 rows are each subjected to a second cyclic shift to obtain a tenth matrices.

19. The method according to claim 18, characterized in that, The first row to the Qth row of each of the a twelfth matrices m The -1 rows are each subjected to a second cyclic shift to obtain a tenth matrices, including: According to K seg And the row number q, determine the fourth value; Based on the fourth value, the second cyclic shift is performed on the q-th row of each of the a twelfth matrices to obtain a tenth matrices. Where 1≤K seg <C, 0≤q≤Q m -1, q, and K seg All are positive integers.

20. The method according to claim 18, characterized in that, At least two of the C seventh-bit sequences are co-coded. The first row to the Qth row of each of the a twelfth matrices m The -1 rows are each subjected to a second cyclic shift to obtain a tenth matrices, including: The fifth value is determined based on the window length w and row number q corresponding to the C seventh bit sequences; Based on the fifth value, the second cyclic shift is performed on the q-th row of each of the a twelfth matrices to obtain a tenth matrices. Where 0≤q≤Q m -1, where q and w are both positive integers.

21. A communication device, characterized in that, The apparatus includes: a module for performing the method as described in any one of claims 1 to 6, or a module for performing the method as described in any one of claims 7 to 12, or a module for performing the method as described in any one of claims 13 to 16, or a module for performing the method as described in any one of claims 17 to 20.

22. A communication device, characterized in that, include: A processor is configured to execute a computer program stored in a memory to cause the apparatus to perform the method as claimed in any one of claims 1 to 6, or to cause the apparatus to perform the method as claimed in any one of claims 7 to 12, or to cause the apparatus to perform the method as claimed in any one of claims 13 to 16, or to cause the apparatus to perform the method as claimed in any one of claims 17 to 20.

23. A computer program product, characterized in that, The computer program product includes instructions for performing the method as described in any one of claims 1 to 6, or the computer program product includes instructions for performing the method as described in any one of claims 7 to 12, or the computer program product includes instructions for performing the method as described in any one of claims 13 to 16, or the computer program product includes instructions for performing the method as described in any one of claims 17 to 20.

24. A computer-readable storage medium, characterized in that, include: The computer-readable storage medium stores a computer program; when the computer program is run on a computer, it causes the computer to perform the method as described in any one of claims 1 to 6, or to perform the method as described in any one of claims 7 to 12, or to perform the method as described in any one of claims 3 to 16, or to perform the method as described in any one of claims 17 to 20.

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