Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device having micro-sized transistors. The semiconductor device has three vertical transistors (first transistor to third transistor). The second transistor and the third transistor are disposed on the first transistor. The second transistor is provided so as to have a region overlapping with the first transistor, and one of a source electrode and a drain electrode of the second transistor and one of a source electrode and a drain electrode of the first transistor are connected. The second transistor and the third transistor are connected in series with each other.

Description

Semiconductor device and method for manufacturing the same 【0001】 One aspect of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. One aspect of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device. 【0002】 Note that one aspect of the present invention is not limited to the above technical field. As the technical field of one aspect of the present invention, semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices having them, their driving methods, or their manufacturing methods can be cited as an example. 【0003】 In the present specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip provided with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device are semiconductor devices themselves and may each have a semiconductor device. 【0004】 A semiconductor device having a transistor is widely applied to display devices and electronic devices, and high integration and high speed of semiconductor devices are required. For example, when applying a semiconductor device to a high-definition display device, a semiconductor device with a high integration degree is required. As one means for increasing the integration degree of a transistor, the development of transistors with a fine size is in progress. 【0005】In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitute reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproduction in order to enhance the sense of reality and immersion. Examples of such display devices include liquid crystal displays, organic EL (Electroluminescence) devices, and light-emitting devices (also called light-emitting elements) such as light-emitting diodes (LEDs). 【0006】 Patent Document 1 discloses a display device for VR using an organic EL device (also called an organic EL element). 【0007】 International Publication No. 2018 / 087625 【0008】 One aspect of the present invention aims to provide a semiconductor device having a minutely sized transistor and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a miniature semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a large on-current and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a highly integrated semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a high-resolution display device. 【0009】 Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims. 【0010】 To further increase the integration of semiconductor devices, it is effective to miniaturize the transistors in the device and to devise a better layout for them. For example, instead of arranging multiple transistors in a semiconductor device on the same plane, it is effective to stack them perpendicular to the substrate surface. This allows for higher integration of the semiconductor device without increasing the area occupied by the transistors on the substrate surface. 【0011】One aspect of the Future comprises a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first transistor comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer, the second transistor comprises a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a fifth insulating layer, and the third transistor comprises a third semiconductor layer, a seventh conductive layer, a fifth conductive layer, and a sixth conductive layer. The semiconductor has a fifth insulating layer, the first insulating layer is provided on the first conductive layer, the second conductive layer is provided on the first insulating layer, the first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer, within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer and the side surface of the second conductive layer, the fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, and the third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening, and the second An insulating layer is provided on the third conductive layer so as to fill the first opening, a fourth conductive layer is provided on the second insulating layer so as to have a region overlapping with the first transistor, a seventh conductive layer is provided on the second insulating layer in a region different from the fourth conductive layer, a third insulating layer is provided on the fourth conductive layer and the seventh conductive layer, a fifth conductive layer is provided on the third insulating layer, and the third insulating layer and the fifth conductive layer have a second opening that reaches the fourth conductive layer and a third opening that reaches the seventh conductive layer, and the second opening Within the semiconductor device, the second semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the third insulating layer, and the side surface of the fifth conductive layer. Within the third opening, the third semiconductor layer is provided in contact with the upper surface of the seventh conductive layer, the side surface of the third insulating layer, and the side surface of the fifth conductive layer. The fifth insulating layer is provided in contact with the upper surface of the second semiconductor layer and the upper surface of the third semiconductor layer, respectively. The sixth conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has regions that overlap with the second opening and the third opening, respectively. 【0012】Furthermore, in the above, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each oxide semiconductor layers having indium, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the third insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have silicon and nitrogen, the seventh insulating layer and the tenth insulating layer each have silicon and oxygen, and the second insulating layer preferably has one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. 【0013】 Furthermore, in the above, it is preferable that the fourth insulating layer and the second insulating layer have a fourth opening that reaches the second conductive layer, and that an eighth conductive layer is provided so as to fill the fourth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the fourth conductive layer, respectively. 【0014】 Furthermore, in the above, it is preferable that the first insulating layer, the fourth insulating layer, and the second insulating layer each have a fifth opening that reaches the first conductive layer, and that an eighth conductive layer is provided so as to fill the fifth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the fourth conductive layer, respectively. 【0015】Furthermore, one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer, the second transistor has a second semiconductor layer, a first conductive layer, a fourth conductive layer, a third conductive layer, and a fourth insulating layer, and the third transistor has a third semiconductor layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer. The semiconductor layer comprises a first insulating layer, a second conductive layer and a fourth conductive layer, each provided in different regions on the first insulating layer, the first insulating layer and the second conductive layer having a first opening reaching the first conductive layer, the first insulating layer and the fourth conductive layer having a second opening reaching the first conductive layer, the first semiconductor layer being provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer and the side surface of the second conductive layer within the first opening, and the second semiconductor layer being provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer and the side surface of the second conductive layer within the second opening. The fourth conductive layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the fourth conductive layer, and the fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer and the upper surface of the second semiconductor layer, respectively. The third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening and the second opening, respectively. The second insulating layer is provided on the third conductive layer so as to fill the first opening and the second opening, respectively. The fifth conductive layer is provided on the second insulating layer such that it has a region that overlaps with the first transistor. A semiconductor device is provided in layers, the third insulating layer is provided on the fifth conductive layer, the sixth conductive layer is provided on the third insulating layer, the third insulating layer and the sixth conductive layer have a third opening that reaches the fifth conductive layer, and within the third opening, the third semiconductor layer is provided in contact with the upper surface of the fifth conductive layer, the side surface of the third insulating layer and the side surface of the sixth conductive layer, the fifth insulating layer is provided in contact with the upper surface of the third semiconductor layer, and the seventh conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has a region that overlaps with the third opening. 【0016】Furthermore, in the above, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each oxide semiconductor layers having indium, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the third insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have silicon and nitrogen, the seventh insulating layer and the tenth insulating layer each have silicon and oxygen, and the second insulating layer preferably has one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. 【0017】 Furthermore, in the above, it is preferable that the fourth insulating layer and the second insulating layer have a fourth opening that reaches the second conductive layer, and that an eighth conductive layer is provided so as to fill the fourth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the fifth conductive layer, respectively. 【0018】 Furthermore, in the above, it is preferable that the fourth insulating layer, the second insulating layer, and the third insulating layer each have a fifth opening that reaches the second conductive layer, and that an eighth conductive layer is provided so as to fill the fifth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the sixth conductive layer, respectively. 【0019】Furthermore, one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer, the second transistor has a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a fifth insulating layer, and the third transistor has a third semiconductor layer, a fourth conductive layer, a seventh conductive layer, and a sixth insulating layer. The semiconductor has a conductive layer and a fifth insulating layer, the first insulating layer is provided on the first conductive layer, the second conductive layer is provided on the first insulating layer, the first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer, within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer and the side surface of the second conductive layer, the fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, and the third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening The second insulating layer is provided on the third conductive layer so as to fill the first opening, the fourth conductive layer is provided on the second insulating layer so as to have a region that overlaps with the first transistor, the third insulating layer is provided on the fourth conductive layer, the fifth conductive layer and the seventh conductive layer are each provided in different regions on the third insulating layer, the third insulating layer and the fifth conductive layer have a second opening that reaches the fourth conductive layer, the third insulating layer and the seventh conductive layer have a third opening that reaches the fourth conductive layer, and within the second opening In this semiconductor device, the second semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the third insulating layer, and the side surface of the fifth conductive layer. Within the third opening, the third semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the third insulating layer, and the side surface of the seventh conductive layer. The fifth insulating layer is provided in contact with the upper surface of the second semiconductor layer and the upper surface of the third semiconductor layer, respectively. The sixth conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has regions that overlap with the second opening and the third opening, respectively. 【0020】Furthermore, in the above, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each oxide semiconductor layers having indium, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the third insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have silicon and nitrogen, the seventh insulating layer and the tenth insulating layer each have silicon and oxygen, and the second insulating layer preferably has one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. 【0021】 Furthermore, in the above, it is preferable that the fourth insulating layer, the second insulating layer, and the third insulating layer each have a fourth opening that reaches the second conductive layer, and that an eighth conductive layer is provided so as to fill the fourth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the fifth conductive layer, respectively. 【0022】 Furthermore, in the above, it is preferable that the first insulating layer, the fourth insulating layer, the second insulating layer, and the third insulating layer each have a fifth opening that reaches the first conductive layer, and that an eighth conductive layer is provided so as to fill the fifth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the fifth conductive layer, respectively. 【0023】Furthermore, one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer, the second transistor has a second semiconductor layer, a fourth conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer, and the third transistor has a third semiconductor layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a fifth conductive layer. The semiconductor has an insulating layer and a second conductive layer, the first conductive layer and the fourth conductive layer are each provided in different regions on the same plane, the first insulating layer is provided on the first conductive layer and the fourth conductive layer, the second conductive layer is provided on the first insulating layer, the first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer and a second opening that reaches the fourth conductive layer, within the first opening the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer and the side surface of the second conductive layer, and within the second opening the second The semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer, the fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer and the upper surface of the second semiconductor layer, the third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening and the second opening, the second insulating layer is provided on the third conductive layer such that it fills the first opening and the second opening, and the fifth conductive layer is provided on the second such that it has a region that overlaps with the first transistor. A semiconductor device is provided on an insulating layer, a third insulating layer is provided on a fifth conductive layer, a sixth conductive layer is provided on a third insulating layer, the third insulating layer and the sixth conductive layer have a third opening that reaches the fifth conductive layer, and within the third opening, the third semiconductor layer is provided in contact with the upper surface of the fifth conductive layer, the side surface of the third insulating layer, and the side surface of the sixth conductive layer, the fifth insulating layer is provided in contact with the upper surface of the third semiconductor layer, and the seventh conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has a region that overlaps with the third opening. 【0024】Furthermore, in the above, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each oxide semiconductor layers having indium, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the third insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have silicon and nitrogen, the seventh insulating layer and the tenth insulating layer each have silicon and oxygen, and the second insulating layer preferably has one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. 【0025】 Furthermore, in the above, it is preferable that the first insulating layer, the fourth insulating layer, and the second insulating layer each have a fourth opening that reaches the first conductive layer, and that an eighth conductive layer is provided so as to fill the fourth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the fifth conductive layer, respectively. 【0026】 Furthermore, in the above, it is preferable that the first insulating layer, the fourth insulating layer, the second insulating layer, and the third insulating layer each have a fifth opening that reaches the first conductive layer, and that an eighth conductive layer is provided so as to fill the fifth opening, and that the eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the sixth conductive layer, respectively. 【0027】Furthermore, in one aspect of the present invention, a first conductive layer, a first insulating film, and a first conductive film are formed in this order, a portion of the first insulating film and the first conductive film is removed to form a first opening that reaches the first conductive layer, and a first insulating layer and a second conductive layer are formed, and within the first opening, a first semiconductor layer is formed in contact with the side surface of the second conductive layer, the side surface of the first insulating layer, and the upper surface of the first conductive layer, and a second insulating layer is formed in contact with the upper surface of the first semiconductor layer. A third conductive layer is formed in contact with the upper surface of the second insulating layer so as to have a region that overlaps with the first opening, a third insulating layer is formed on the third conductive layer so as to fill the first opening, a second opening is formed by removing a part of the third insulating layer to reach the second conductive layer, a fourth conductive layer is formed in contact with the upper surface of the second conductive layer so as to fill the second opening, and a fifth conductive layer is formed on the third insulating layer so as to have a region that contacts the upper surface of the fourth conductive layer, This is a method for manufacturing a semiconductor device, comprising: forming a sixth conductive layer in a region on a third insulating layer different from the fifth conductive layer; forming a second insulating film and a second conductive film on the fifth conductive layer and the sixth conductive layer in that order; removing a portion of each of the second insulating film and the second conductive film to form a second opening reaching the fifth conductive layer and a third opening reaching the sixth conductive layer, and forming a fourth insulating layer and a seventh conductive layer; forming a second semiconductor layer within the second opening in contact with the side surface of the seventh conductive layer, the side surface of the fourth insulating layer, and the upper surface of the fifth conductive layer; forming a third semiconductor layer within the third opening in contact with the side surface of the seventh conductive layer, the side surface of the fourth insulating layer, and the upper surface of the sixth conductive layer; forming a fifth insulating layer in contact with the upper surface of the second semiconductor layer and the upper surface of the third semiconductor layer; and forming an eighth conductive layer in contact with the upper surface of the fifth insulating layer so as to have a region overlapping with the second opening and the third opening. 【0028】According to one aspect of the present invention, a semiconductor device having a minutely sized transistor and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a miniature semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a large on-current and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good electrical characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a highly integrated semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a high-definition display device can be provided. 【0029】 Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims. 【0030】Figure 1A is a plan view showing an example of a semiconductor device. Figure 1B is a cross-sectional view showing an example of a semiconductor device. Figure 2A is a plan view showing an example of a semiconductor device. Figure 2B is a cross-sectional view showing an example of a semiconductor device. Figures 3A and 3B are circuit diagrams illustrating a semiconductor device. Figure 4A is a cross-sectional view showing an example of a semiconductor device. Figure 4B is a circuit diagram illustrating a semiconductor device. Figure 5A is a cross-sectional view showing an example of a semiconductor device. Figure 5B is a circuit diagram illustrating a semiconductor device. Figure 6A is a cross-sectional view showing an example of a semiconductor device. Figure 6B is a circuit diagram illustrating a semiconductor device. Figure 7A is a cross-sectional view showing an example of a semiconductor device. Figure 7B is a circuit diagram illustrating a semiconductor device. Figure 8A is a cross-sectional view showing an example of a semiconductor device. Figure 8B is a circuit diagram illustrating a semiconductor device. Figure 9A is a cross-sectional view showing an example of a semiconductor device. Figure 9B is a circuit diagram illustrating a semiconductor device. Figure 10A is a cross-sectional view showing an example of a semiconductor device. Figure 10B is a circuit diagram illustrating a semiconductor device. Figure 11A is a cross-sectional view showing an example of a semiconductor device. Figure 11B is a circuit diagram illustrating a semiconductor device. Figures 12A and 12B are cross-sectional views showing an example of a semiconductor device. Figure 13A is a plan view showing an example of a semiconductor device manufacturing method. Figure 13B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figure 14B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figure 15B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figure 16B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figure 17B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figure 18B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 19A is a plan view showing an example of a semiconductor device manufacturing method. Figure 19B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 20A is a plan view showing an example of a semiconductor device manufacturing method.Figure 20B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 21A is a plan view showing an example of a semiconductor device manufacturing method. Figure 21B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 22A is a plan view showing an example of a semiconductor device manufacturing method. Figure 22B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 23A is a plan view showing an example of a semiconductor device manufacturing method. Figure 23B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 24A is a plan view showing an example of a semiconductor device manufacturing method. Figure 24B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 25A is a plan view showing an example of a semiconductor device manufacturing method. Figure 25B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 26A is a plan view showing an example of a semiconductor device manufacturing method. Figure 26B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 27A is a plan view showing an example of a semiconductor device manufacturing method. Figure 27B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 28 is a block diagram of a display device. Figures 29A and 29B are circuit diagrams of pixel circuits. Figures 30A, 30B, and 30C are circuit diagrams of pixel circuits. Figures 31A and 31B are plan views showing an example of a semiconductor device fabrication method. Figures 32A and 32B are plan views showing an example of a semiconductor device fabrication method. Figures 33A and 33B are plan views showing an example of a semiconductor device fabrication method. Figures 34A and 34B are plan views showing an example of a semiconductor device fabrication method. Figures 35A and 35B are plan views showing an example of a semiconductor device fabrication method. Figures 36A and 36B are plan views showing an example of a semiconductor device fabrication method. Figures 37A and 37B are plan views showing an example of a semiconductor device fabrication method. Figures 38A and 38B are plan views showing an example of a semiconductor device fabrication method. Figures 39A and 39B are plan views showing an example of a semiconductor device fabrication method. Figures 40A and 40B are plan views showing an example of a semiconductor device fabrication method. Figures 41A and 41B are plan views showing an example of a semiconductor device fabrication method. Figures 42A and 42B are plan views showing an example of a semiconductor device manufacturing method. Figures 43A and 43B are plan views showing an example of a semiconductor device manufacturing method.Figures 44A and 44B are plan views showing an example of a semiconductor device manufacturing method. Figures 45A and 45B are plan views showing an example of a semiconductor device manufacturing method. Figures 46A and 46B are plan views showing an example of a semiconductor device manufacturing method. Figures 47A and 47B are plan views showing an example of a semiconductor device manufacturing method. Figures 48A and 48B are plan views showing an example of a semiconductor device manufacturing method. Figures 49A and 49B are plan views showing an example of a semiconductor device manufacturing method. Figures 50A and 50B are plan views showing an example of a semiconductor device manufacturing method. Figures 51A and 51B are plan views showing an example of a semiconductor device manufacturing method. Figures 52A and 52B are plan views showing an example of a semiconductor device manufacturing method. Figures 53A and 53B are plan views showing an example of a semiconductor device. Figures 54A and 54B are plan views showing an example of a semiconductor device. Figure 55 is a perspective view showing an example of a display device. Figure 56 is a cross-sectional view showing an example of a display device. Figure 57 is a cross-sectional view showing an example of a display device. Figure 58 is a cross-sectional view showing an example of a display device. Figure 59 is a cross-sectional view showing an example of a display device. Figures 60A, 60B, 60C, and 60D are diagrams showing an example of an electronic device. Figures 61A, 61B, 61C, 61D, 61E, and 61F are diagrams showing an example of an electronic device. Figures 62A, 62B, 62C, 62D, 62E, 62F, and 62G are diagrams showing an example of an electronic device. 【0031】 Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below. 【0032】Furthermore, the ordinal numbers "first," "second," and "third" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. 【0033】 In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned. 【0034】 The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings. 【0035】 It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer." 【0036】 A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs). 【0037】The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, etc., depending on the situation. 【0038】 The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" can be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as needed, such as gate electrode and back gate electrode. 【0039】 In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers. 【0040】 For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected." 【0041】 An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected." 【0042】 Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc. 【0043】 In this specification, a structure in which at least the light-emitting layers are created separately for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and configuration for each light-emitting device, it increases the degree of freedom in selecting materials and configurations, making it easier to improve brightness and reliability. 【0044】 In this specification, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole block layer or electron block layer may be called a "carrier block layer." It should be noted that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable by their cross-sectional shape or characteristics. Furthermore, a single layer may combine the functions of two or three of these layers. 【0045】In this specification, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. The layers (also called functional layers) of the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). 【0046】 In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated. 【0047】 In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it refers to a shape having a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities. 【0048】 In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (for example, a step or other difference in height). 【0049】 In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less. 【0050】In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching." 【0051】 In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed. 【0052】 Furthermore, in this specification, "approximately matching height" refers to a configuration in which the height from a reference surface (for example, a flat surface such as the substrate surface) is approximately equal in a cross-sectional view. For example, when a planarization treatment (typically chemical mechanical polishing (CMP) treatment) is performed, the treated surface will have approximately matching height. However, even after a planarization treatment, the height may not be exactly the same depending on the film material, but in this specification, this is also considered to be "approximately matching height". 【0053】 (Embodiment 1) This embodiment describes a semiconductor device, a method for manufacturing a semiconductor device, and the like according to one aspect of the present invention. 【0054】 One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. 【0055】The first to third transistors are all vertical transistors in which the source electrode and drain electrode are provided at different heights relative to the substrate surface, and the drain current flows in the vertical direction. Therefore, miniaturization and reduction of the occupied area can be achieved compared to planar transistors in which the source electrode and drain electrode are provided on the same plane. The first to third transistors having the above-described structure enable miniaturization and high integration of the semiconductor device. 【0056】 Herein, in each of the first to third transistors, the electrode located closer to the substrate surface will be referred to as "one of the source electrodes or drain electrodes," and the electrode located further away from the substrate surface will be referred to as "the other of the source electrode or drain electrode." 【0057】 The second transistor is stacked on top of the first transistor. Therefore, the semiconductor device can be miniaturized and highly integrated compared to the case where the first and second transistors are located on the same plane. 【0058】 It is preferable that the first transistor and the second transistor are arranged so as to have overlapping regions. Furthermore, it is preferable that the area of ​​the overlapping region of the first transistor and the second transistor is large. This allows for a further reduction in the area occupied by the semiconductor device, thereby enabling further integration of the semiconductor device. 【0059】 The third transistor is located adjacent to the second transistor. The second and third transistors share some components. 【0060】 The first insulating layer is provided so as to have a region sandwiched between the source electrode and the drain electrode of the first transistor. The second insulating layer is provided so as to cover the first transistor and has a flat upper surface. The third insulating layer is provided so as to have a region sandwiched between the source electrode and the drain electrode of the second transistor, and between the source electrode and the drain electrode of the third transistor. 【0061】 The second transistor can also be described as being provided on the first transistor via a second insulating layer. The first conductive layer is provided so as to be embedded in the second insulating layer. The first conductive layer has regions that are in contact with the upper surface of the other source electrode or drain electrode of the first transistor, and the lower surface of one of the source electrode or drain electrode of the second transistor, respectively. 【0062】 A first opening is provided in the source electrode or drain electrode of the first transistor, and in the first insulating layer, reaching either the source electrode or drain electrode of the first transistor. The first transistor is provided with a semiconductor layer that functions as a channel forming region, in contact with the source electrode and the drain electrode, so as to encompass the first opening. 【0063】 A second opening is provided in the source electrode or drain electrode of the second transistor, and in the third insulating layer, reaching either the source electrode or drain electrode of the second transistor. The second transistor is provided with a semiconductor layer that functions as a channel forming region, in contact with the source electrode and the drain electrode, so as to encompass the second opening. 【0064】 A third opening is provided in the source electrode or drain electrode of the third transistor, and in the third insulating layer, reaching either the source electrode or drain electrode of the third transistor. The third transistor is provided with a semiconductor layer that functions as a channel forming region, in contact with the source electrode and the drain electrode, so as to encompass the third opening. 【0065】 Here, the conductive layer that functions as the other source or drain electrode of the second transistor can also function as the other source or drain electrode of the third transistor. That is, the second transistor and the third transistor share the other source or drain electrode. 【0066】Furthermore, the insulating layer that functions as the gate insulating layer of the second transistor can also function as the gate insulating layer of the third transistor. In other words, the second transistor and the third transistor share a gate insulating layer. 【0067】 Furthermore, the conductive layer that functions as the gate electrode of the second transistor can also function as the gate electrode of the third transistor. In other words, the second transistor and the third transistor share a gate electrode. 【0068】 In other words, the second transistor and the third transistor can be said to be connected in series with each other. A configuration in which two transistors are connected in series can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of the two transistors. Therefore, by connecting the second and third transistors in series, the overall channel length of the transistor can be made longer than in the case of using only one transistor, and the current saturation can be improved (i.e., the change in current in the saturation region of the transistor's drain current (Id) - drain voltage (Vd) characteristic can be reduced). 【0069】 For example, by applying a second and third transistor connected in series to the drive transistor included in the pixel circuit of a display device using an organic EL device, a drive transistor with excellent current saturation can be created. This stabilizes the luminescence brightness of the light-emitting device, thereby enabling the realization of a display device with extremely low display uniformity. 【0070】 As described above, in one embodiment of the present invention, vertical transistors are used for all of the first to third transistors in the semiconductor device. Therefore, even when multiple transistors are arranged adjacent to each other on the same plane, such as the second and third transistors, the occupied area of ​​the semiconductor device can be significantly reduced compared to when planar transistors are used. Furthermore, the occupied area of ​​the semiconductor device can be further reduced by stacking the first transistor on the lower layer of the second and third transistors. 【0071】 The above description concerns a configuration in which a second and third transistor, connected in series, are stacked on top of a first transistor; however, this is not the only configuration. One embodiment of the present invention also includes a configuration in which the first transistor is stacked on top of a second and third transistor, which are connected in series. As long as the overall circuit connection configuration of the semiconductor device remains unchanged, the first transistor can be placed below or above the second and third transistors. In either case, the above-mentioned effects can be enjoyed equally. 【0072】 In this way, by configuring the first to third transistors as described above, it is possible to realize an extremely compact semiconductor device with high integration density and excellent electrical characteristics. 【0073】 For example, by using a semiconductor device according to one aspect of the present invention in the pixel circuit of a display device, an extremely high-resolution and high-quality display device can be realized. 【0074】 In the following section, a specific example of the configuration of a semiconductor device according to one aspect of the present invention will be described with reference to the drawings. 【0075】 <Example of Semiconductor Device Configuration 1> Figure 1A shows a plan view (also called a top view) of the semiconductor device 100. Figure 1B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 1A. Figure 3A shows an equivalent circuit diagram of the semiconductor device 100. Note that in Figure 1A, some of the components of the semiconductor device 100 (such as the insulating layer) are omitted. In subsequent drawings of semiconductor devices, some of the components may also be omitted, similar to Figure 1A. 【0076】The semiconductor device 100 is provided on a substrate 102. Although not shown in Figure 1B, etc., an insulating layer functioning as an underlayment may be provided between the substrate 102 and the semiconductor device 100. The semiconductor device 100 includes a transistor 10_1, a transistor 10_2A, a transistor 10_2B, an insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1), an insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), an insulating layer 192, an insulating layer 193, an insulating layer 194, and a conductive layer 115. Transistors 10_1 and 10_2A are provided superimposed in this order. Transistor 10_2B is provided adjacent to transistor 10_2A. Transistors 10_2A and 10_2B share some components. 【0077】 The transistor 10_1 has a conductive layer 104_1, an insulating layer 106_1, a semiconductor layer 108_1, a conductive layer 112a1, and a conductive layer 112b1. The conductive layer 104_1 functions as a gate electrode. A portion of the insulating layer 106_1 functions as a gate insulating layer. The conductive layer 112a1 functions as either a source electrode or a drain electrode. The conductive layer 112b1 functions as either a source electrode or a drain electrode. Of the semiconductor layer 108_1, the entire region that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode functions as a channel forming region. Furthermore, of the semiconductor layer 108_1, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region. 【0078】 The above explanation relating to transistor 10_1 can be applied to transistor 10_2A by replacing the conductive layer 104_1, insulating layer 106_1, semiconductor layer 108_1, conductive layer 112a1, and conductive layer 112b1 with conductive layer 104_2, insulating layer 106_2, semiconductor layer 108_2A, conductive layer 112a2A, and conductive layer 112b2, respectively. 【0079】Similarly, the above explanation relating to transistor 10_1 can be applied to transistor 10_2B by replacing the conductive layer 104_1, insulating layer 106_1, semiconductor layer 108_1, conductive layer 112a1, and conductive layer 112b1 with conductive layer 104_2, insulating layer 106_2, semiconductor layer 108_2B, conductive layer 112a2B, and conductive layer 112b2, respectively. 【0080】 In other words, the conductive layer 112b2 functions as the other source electrode or drain electrode of transistor 10_2A, and can also function as the other source electrode or drain electrode of transistor 10_2B. The insulating layer 106_2 functions as the gate insulating layer of transistor 10_2A, and can also function as the gate insulating layer of transistor 10_2B. The conductive layer 104_2 functions as the gate electrode of transistor 10_2A, and can also function as the gate electrode of transistor 10_2B. 【0081】 Therefore, transistor 10_2A and transistor 10_2B can be said to be connected in series with each other. Transistors 10_2A and 10_2B connected in series can be considered as a single transistor whose channel length is the sum of the channel lengths of each transistor. Since this single transistor has a longer channel length than each of transistors 10_2A and 10_2B, it can be a transistor with higher current saturation than each of transistors 10_2A and 10_2B. 【0082】 The detailed configuration of the semiconductor device 100 will now be described. 【0083】 A conductive layer 112a1 is provided on the substrate 102. An insulating layer 110a1 is provided on the conductive layer 112a1. An insulating layer 110b1 is provided on the insulating layer 110a1. An insulating layer 110c1 is provided on the insulating layer 110b1. A conductive layer 112b1 is provided on the insulating layer 110c1. Note that insulating layers 110a1, 110b1, and 110c1 are sometimes collectively referred to as insulating layer 110_1. 【0084】The conductive layer 112a1, the insulating layer 110_1, and the conductive layer 112b1 have overlapping regions. In these regions, the insulating layer 110_1 is provided so as to be sandwiched between the conductive layer 112a1 and the conductive layer 112b1. 【0085】 The insulating layer 110_1 and the conductive layer 112b1 have openings 143 that reach the conductive layer 112a1. 【0086】 The top surface shape of the opening 143 can be, for example, circular or elliptical. The top surface shape of the opening 143 can also be a polygon such as a triangle, quadrilateral (including rectangle, rhombus, and square), pentagon, or a polygon with rounded corners. As shown in Figure 1A, the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and a fine-sized opening 143 can be formed. In this specification, the term "circular" is not limited to a perfect circle. 【0087】 Note that while Figure 1B shows a configuration where the film thickness in the region overlapping the opening 143 of the conductive layer 112a1 is approximately equal to the film thickness in the region not overlapping the opening 143, this is not limited to this configuration. The film thickness in the region overlapping the opening 143 of the conductive layer 112a1 can be thinner than the film thickness in the region not overlapping the opening 143. In this case, the electric field from the conductive layer 104_1 (i.e., the gate electric field of transistor 10_1) can be applied to the channel formation region near the conductive layer 112a1. Therefore, it may be possible to strengthen the effect of the gate electric field on carriers in the channel formation region compared to the case where the film thickness of the conductive layer 112a1 is uniform. 【0088】 A semiconductor layer 108_1 is provided in contact with the upper surface of the conductive layer 112a1 within the opening 143, the side surface of the insulating layer 110_1 within the opening 143, the side surface of the conductive layer 112b1 within the opening 143, and the upper surface of the conductive layer 112b1. 【0089】Although Figure 1B shows a configuration in which the semiconductor layer 108_1 has a region in contact with the upper surface of the conductive layer 112b1, this is not the only configuration. The semiconductor layer 108_1 only needs to have a region in contact with the side surface of the conductive layer 112b1 within the opening 143. 【0090】 For example, by configuring the entire area of ​​the semiconductor layer 108_1 to be located within the opening 143, and the edges of the semiconductor layer 108_1 to be in contact only with the side surface of the conductive layer 112b1 within the opening 143, it is possible to suppress the occurrence of a step on the conductive layer 112b1 due to the edges of the semiconductor layer 108_1. This makes it possible to improve the coverage of the film that has the upper surface of the conductive layer 112b1 as the surface to be formed. 【0091】 On the other hand, as shown in Figure 1B, by having the end of the semiconductor layer 108_1 extend to the outside of the opening 143, and configuring the semiconductor layer 108_1 to contact not only the side surface of the conductive layer 112b1 within the opening 143 but also the upper surface of the conductive layer 112b1, the contact area between the semiconductor layer 108_1 and the conductive layer 112b1 can be increased. This can suppress delamination of the semiconductor layer 108_1. In addition, the contact resistance between the semiconductor layer 108_1 and the conductive layer 112b1 becomes smaller, which may allow the on-current of the transistor 10_1 to be increased. 【0092】 Here, it is preferable that the insulating layer 110b1 of the insulating layer 110_1 is an insulating layer containing oxygen. Furthermore, it is preferable that it is an insulating layer that releases oxygen when heated. This allows, for example, when a metal oxide is used for the semiconductor layer 108_1, the oxygen contained in the insulating layer 110b1 to be supplied to the metal oxide. This allows oxygen deficiencies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of the transistor 10_1. 【0093】On the other hand, among the insulating layers 110_1, it is preferable that insulating layers 110a1 and 110c1 are insulating layers that have barrier properties against gases such as oxygen and hydrogen. This makes it possible to suppress the release of oxygen contained in insulating layer 110b1 to the outside through insulating layer 110a1 or insulating layer 110c1. Furthermore, it is possible to suppress the diffusion of hydrogen from outside the insulating layer 110_1 into insulating layer 110b1 through insulating layer 110a1 or insulating layer 110c1, and the diffusion of said hydrogen into semiconductor layer 108_1. For example, when a metal oxide is used for semiconductor layer 108_1, hydrogen in semiconductor layer 108_1 can be a factor that degrades the electrical characteristics and reliability of transistor 10_1. 【0094】 In this specification, "barrier property" refers to the function of suppressing the diffusion of the corresponding substance (also known as low permeability). Alternatively, it refers to the function of capturing or fixing the corresponding substance (also known as gettering). In this specification, an insulating layer having barrier properties may be referred to as a barrier insulating layer. 【0095】 An insulating layer 106_1 is provided on the semiconductor layer 108_1. The insulating layer 106_1 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_1, the upper and side surfaces of the conductive layer 112b1, and the upper surface of the insulating layer 110c1. 【0096】 A conductive layer 104_1 is provided on the insulating layer 106_1. The conductive layer 104_1 is provided in contact with the upper surface of the insulating layer 106_1 such that, in a plan view, it has a region that overlaps with the opening 143. Within the opening 143, the conductive layer 104_1 has a shape that conforms to the shapes of the semiconductor layer 108_1 and the insulating layer 106_1. That is, the conductive layer 104_1 has a recess on its upper surface that corresponds to the shape of the opening 143. Within the opening 143, the conductive layer 104_1 has a region that faces the semiconductor layer 108_1 via the insulating layer 106_1. 【0097】Furthermore, the conductive layer 104_1 can also be formed to embed the opening 143. For example, depending on the depth of the opening 143 or the size of its diameter in a plan view (specifically, when the aspect ratio of the opening 143 is small), the conductive layer 104_1 may be formed to be embedded in the opening 143. In this case, the step or unevenness formed on the upper surface of the conductive layer 104_1 in the region overlapping with the opening 143 is reduced, which is preferable because it improves the coverage of the layer formed on top of it. 【0098】 An insulating layer 192 is provided on the conductive layer 104_1. The insulating layer 192 has regions that are in contact with the upper surface and side surfaces of the conductive layer 104_1, as well as the upper surface of the insulating layer 106_1. 【0099】 An insulating layer 193 is provided on the insulating layer 192 so as to fill the opening 143. The insulating layer 193 has the function of filling in and flattening steps or irregularities caused by the transistor 10_1. The upper surface of the insulating layer 193 has a generally flat shape. For the insulating layer 193, it is preferable to use, for example, an organic insulating material. This makes it possible to easily and productively flatten the recesses that have formed in the conductive layer 104_1. 【0100】 Preferably, the upper surface of the insulating layer 193 is higher than the upper surface of the highest region of the insulating layer 192 as viewed from the substrate surface. Alternatively, it is preferable that the upper surface of the insulating layer 193 is approximately the same height as the upper surface of the highest region of the insulating layer 192 as viewed from the substrate surface. This makes it possible to form a generally flat surface on which a layer (for example, a conductive layer 112a2A) is formed on the insulating layer 193, thereby improving the coverage of the layer. 【0101】 An insulating layer 194 is provided on the insulating layer 193. The insulating layer 194 has a region that is in contact with the upper surface of the insulating layer 193. 【0102】It is preferable to use the same materials for insulating layer 192 and insulating layer 194 as for insulating layer 110a1 and insulating layer 110c1, respectively. This makes it possible to suppress the diffusion of impurities such as hydrogen into transistor 10_1 from the layer above transistor 10_1 via insulating layer 192. Furthermore, it is possible to suppress the diffusion of impurities such as hydrogen into transistor 10_2A from the layer below transistor 10_2A via insulating layer 194. 【0103】 Furthermore, if there is no concern about the diffusion of the aforementioned impurities, the device can be configured without one or both of the insulating layers 192 and 194. In this case, the number of steps involved in the manufacturing of the semiconductor device 100 can be reduced. 【0104】 The insulating layers 106_1, 192, 193, and 194 are provided with openings 146 that reach the conductive layer 112b1, and the conductive layer 115 is provided so as to fill the openings 146. The conductive layer 115 has a region that is in contact with the upper surface of the conductive layer 112b1. The upper surface of the conductive layer 115 is approximately the same height as the upper surface of the insulating layer 194. The conductive layer 115 functions as a plug that connects the conductive layer 112b1 of transistor 10_1 and the conductive layer 112a2A of transistor 10_2A. 【0105】 By providing a conductive layer 115 that functions as a plug within the opening 146, the surface to be formed of the transistor 10_2A (in this case, the upper surface of the insulating layer 194 and the upper surface of the conductive layer 115) can be made to have a generally flat shape. Therefore, an extremely small transistor 10_2A can be formed on this surface with high precision. 【0106】In Figure 1A, etc., a configuration is shown in which the conductive layer 112b1, which functions as the other source electrode or drain electrode of transistor 10_1, and the conductive layer 112a2A, which functions as one of the source electrode or drain electrode of transistor 10_2A, are connected via a conductive layer 115 that functions as a plug. However, this is not the only configuration. For example, after forming openings 146 in insulating layers 106_1, 192, 193, and 194, a conductive film that will become the conductive layer 112a2A is formed on the insulating layer 194 so as to fill the openings 146. Subsequently, the conductive film can be processed to form the conductive layer 112a2A. In this case, since the conductive layer 112b1 and the conductive layer 112a2A are in contact within the opening 146, it becomes unnecessary to provide the conductive layer 115, and the number of steps involved in the manufacture of the semiconductor device 100 can be reduced. 【0107】 A conductive layer 112a2A is provided on the conductive layer 115 and the insulating layer 194. The conductive layer 112a2A is provided so as to have a region that overlaps with the conductive layer 115. The lower surface of the conductive layer 112a2A (the surface on the substrate 102 side) has a region that is in contact with the upper surface of the conductive layer 115. 【0108】 It is preferable that the conductive layer 112a2A is provided such that it has a region that overlaps with the opening 143. This allows the transistor 10_2A to be formed superimposed on the transistor 10_1, thereby reducing the area occupied on the substrate surface of the semiconductor device 100. 【0109】 Furthermore, a conductive layer 112a2B is provided in a region on the insulating layer 194 that is different from the region where the conductive layer 112a2A is provided. The conductive layer 112a2A and the conductive layer 112a2B can be formed by processing the same material using the same process. 【0110】An insulating layer 110a2 is provided on the conductive layer 112a2A, on the conductive layer 112a2B, and on the insulating layer 194. An insulating layer 110b2 is provided on the insulating layer 110a2. An insulating layer 110c2 is provided on the insulating layer 110b2. A conductive layer 112b2 is provided on the insulating layer 110c2. Note that insulating layers 110a2, 110b2, and 110c2 are sometimes collectively referred to as insulating layer 110_2. 【0111】 It is preferable to use the same materials for insulating layers 110a2, 110b2, and 110c2 as those used for insulating layers 110a1, 110b1, and 110c1, respectively. This allows, for example, when metal oxides are used for semiconductor layers 108_2A and 108_2B, to supply oxygen from insulating layer 110b2 to the metal oxide. It also prevents oxygen from insulating layer 110b2 from being released to the outside via insulating layer 110a2 or insulating layer 110c2. Furthermore, it prevents hydrogen from diffusing into insulating layer 110b2 from outside insulating layer 110_2 via insulating layer 110a2 or insulating layer 110c2, and prevents that hydrogen from diffusing into semiconductor layers 108_2A and 108_2B, respectively. 【0112】 When hydrogen diffuses into semiconductor layer 108_2A and semiconductor layer 108_2B, the hydrogen reacts with oxygen bonded to metal atoms in semiconductor layer 108_2A and semiconductor layer 108_2B to form water, creating oxygen vacancies (V) in semiconductor layer 108_2A and semiconductor layer 108_2B. Ｏ In some cases, an oxygen vacancy may be formed. Furthermore, a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V) may form. Ｏ (Denoted as H.) Hydrogen functions as a donor, and electrons, which are carriers, may be generated. Therefore, if hydrogen diffuses into semiconductor layer 108_2A and semiconductor layer 108_2B, transistors 10_2A and 10_2B may exhibit normally-on characteristics, leading to a deterioration in reliability. Accordingly, by having insulating layer 110_2 with insulating layer 110a2 and insulating layer 110c2, the occurrence of the above-mentioned problems in transistors 10_2A and 10_2B can be suppressed. 【0113】 The conductive layer 112a2A, the insulating layer 110_2, and the conductive layer 112b2 have overlapping regions. In these regions, the insulating layer 110_2 is provided so as to be sandwiched between the conductive layer 112a2A and the conductive layer 112b2. 【0114】 Similarly, the conductive layer 112a2B, the insulating layer 110_2, and the conductive layer 112b2 have overlapping regions. In these regions, the insulating layer 110_2 is provided so as to be sandwiched between the conductive layer 112a2B and the conductive layer 112b2. 【0115】 The conductive layer 112b2 and the insulating layer 110_2 have an opening 144A that reaches the conductive layer 112a2A and an opening 144B that reaches the conductive layer 112a2B. 【0116】 For the upper surface shapes of openings 144A and 144B, refer to the description relating to the upper surface shape of opening 143. In Figure 1A, the upper surface shapes of openings 144A and 144B are shown as circles. 【0117】 In Figure 1A, the top surfaces of openings 143, 144A, and 144B are all shown as circles of the same diameter, but this is not limited to this. The top surfaces of openings 143, 144A, and 144B can each be circles of different diameters. Furthermore, the top surfaces of openings 143, 144A, and 144B do not need to be uniformly circular; they can be combinations of different shapes from those described above. This increases the degree of freedom in the manufacturing of semiconductor devices. 【0118】 Furthermore, while Figure 1B shows a configuration in which the film thickness in the region of the conductive layer 112a2A overlapping with the opening 144A is approximately equal to the film thickness in the region of the conductive layer 112a2A not overlapping with the opening 144A, this is not limited to this configuration. It is also possible to have a configuration in which the film thickness in the region of the conductive layer 112a2A overlapping with the opening 144A is thinner than the film thickness in the region not overlapping with the opening 144A. The same applies to the relationship between the film thickness of the conductive layer 112a2B and the opening 144B. 【0119】As a result, the effect of the electric field from the conductive layer 104_2 on the carriers in the channel formation region of the semiconductor layer 108_2A can be strengthened compared to when the thickness of the conductive layer 112a2A is uniform. Similarly, the effect of the electric field from the conductive layer 104_2 on the carriers in the channel formation region of the semiconductor layer 108_2B can be strengthened compared to when the thickness of the conductive layer 112a2B is uniform. 【0120】 A semiconductor layer 108_2A is provided in contact with the upper surface of the conductive layer 112a2A within the opening 144A, the side surface of the insulating layer 110_2 within the opening 144A, the side surface of the conductive layer 112b2 within the opening 144A, and the upper surface of the conductive layer 112b2. 【0121】 Furthermore, a semiconductor layer 108_2B is provided in contact with the upper surface of the conductive layer 112a2B within the opening 144B, the side surface of the insulating layer 110_2 within the opening 144B, the side surface of the conductive layer 112b2 within the opening 144B, and the upper surface of the conductive layer 112b2. 【0122】 Note that while Figure 1B shows a configuration in which the semiconductor layer 108_2A has a region in contact with the upper surface of the conductive layer 112b2, this is not the only configuration. The semiconductor layer 108_2A only needs to have a region in contact with the side surface of the conductive layer 112b2 within the opening 144A. Similarly, the semiconductor layer 108_2B only needs to have a region in contact with the side surface of the conductive layer 112b2 within the opening 144B. 【0123】 An insulating layer 106_2 is provided on semiconductor layer 108_2A and semiconductor layer 108_2B. The insulating layer 106_2 is provided so as to cover semiconductor layer 108_2A, semiconductor layer 108_2B, and conductive layer 112b2. The insulating layer 106_2 has regions that are in contact with the upper and side surfaces of semiconductor layer 108_2A, the upper and side surfaces of semiconductor layer 108_2B, the upper and side surfaces of conductive layer 112b2, and the upper surface of insulating layer 110_2. 【0124】A conductive layer 104_2 is provided on the insulating layer 106_2. The conductive layer 104_2 is provided in contact with the upper surface of the insulating layer 106_2 such that, in a plan view, it has regions that overlap with the openings 144A and 144B, respectively. Within the opening 144A, the conductive layer 104_2 has a shape that conforms to the shape of the semiconductor layer 108_2A and the insulating layer 106_2, and within the opening 144B, it has a shape that conforms to the shape of the semiconductor layer 108_2B and the insulating layer 106_2. Within the opening 144A, the conductive layer 104_2 has a region that faces the semiconductor layer 108_2A via the insulating layer 106_2, and within the opening 144B, it has a region that faces the semiconductor layer 108_2B via the insulating layer 106_2. 【0125】 Furthermore, the conductive layer 104_2 can also be formed to embed each of the openings 144A and 144B. For example, depending on the depth of each of the openings 144A and 144B, or the width of each of the openings 144A and 144B in a plan view (specifically, when the aspect ratio of each of the openings 144A and 144B is small), the conductive layer 104_2 may be formed to embed each of the openings 144A and 144B. In this case, the steps or irregularities formed on the upper surface of the conductive layer 104_2 in the region overlapping with each of the openings 144A and 144B become smaller, which is preferable because it can improve the coverage of the layer formed on top of it. 【0126】In transistor 10_1, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, which is the surface to be formed, and the drain current flows perpendicular to or approximately perpendicular to the surface of the substrate 102. Similarly, in transistors 10_2A and 10_2B, the source electrode and drain electrode are positioned at different heights relative to the surface of the insulating layer 194, which is the surface to be formed, and the drain current flows perpendicular to or approximately perpendicular to the surface of the insulating layer 194, etc. That is, in each of transistors 10_1, 10_2A, and 10_2B, the drain current can be said to flow in the vertical direction. Therefore, a transistor according to one aspect of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor). 【0127】 Since transistors 10_1, 10_2A, and 10_2B can all have their source and drain electrodes stacked on top of each other, they can be miniaturized compared to so-called planar transistors where the source and drain electrodes are arranged on the same plane. Furthermore, the area occupied by the transistors on the substrate can be significantly reduced. 【0128】 Furthermore, in one embodiment of the present invention, the semiconductor device 100 has a configuration in which a transistor 10_2A is provided superimposed on a transistor 10_1 whose gate electrode recess, formed by the insulating layer 193, is substantially flattened. As a result, the area occupied by the transistors on the substrate surface can be significantly reduced compared to a configuration in which these two transistors are arranged on the same plane, thereby enabling miniaturization and high integration of the semiconductor device. For example, by using the semiconductor device according to one embodiment of the present invention in the pixel circuit of a display device using an organic EL device, an extremely high-resolution display device can be realized. 【0129】Furthermore, in a semiconductor device 100 according to one aspect of the present invention, a transistor 10_2B is provided adjacent to transistor 10_2A and connected in series with transistor 10_2A. Therefore, the combination of transistor 10_2A and transistor 10_2B can be considered as a single transistor whose channel length is the sum of the channel lengths of the respective transistors. This makes it possible to make this single transistor a transistor with higher current saturation than transistors 10_2A and 10_2B individually. 【0130】 For example, by applying transistors 10_2A and 10_2B to the drive transistors included in the pixel circuit of a display device using an organic EL device, it is possible to create a drive transistor with better current saturation than when transistor 10_2B is not present. This makes it possible to stabilize the luminescence brightness of the light-emitting device, thereby realizing a display device with extremely low display uniformity. 【0131】 Furthermore, the transistors in the semiconductor device 100 according to one aspect of the present invention are all vertical transistors. Therefore, even when transistors 10_2A and 10_2B are provided adjacent to each other on the same plane, a significant increase in occupied area can be suppressed compared to when planar transistors are used. Consequently, even with a configuration having multiple transistors, such as the semiconductor device 100, it is possible to achieve both good electrical characteristics and miniaturization. 【0132】 The channel length and channel width of transistor 10_2B will be described below. Note that the information described below can also be applied to transistors 10_1 and 10_2A, which are also vertical transistors, by appropriately substituting the reference numerals indicating the components of transistor 10_2B. 【0133】In the semiconductor layer 108_2B, the region in contact with the conductive layer 112a2B functions as either a source region or a drain region, the region in contact with the conductive layer 112b2 functions as either a source region or a drain region, and the region between the source region and the drain region functions as a channel-forming region. 【0134】 The channel length of transistor 10_2B is the distance between the source region and the drain region. In Figure 1B, the channel length L10_2B of transistor 10_2B is shown by a dashed double arrow. In Figure 1B, the distance along the semiconductor layer 108_2B in the region between the conductive layer 112a2B and the conductive layer 112b2 is shown as the channel length L10_2B of transistor 10_2B. 【0135】 In addition, the channel length L10_2B of transistor 10_2B may be defined as the thickness of the insulating layer 110_2 in the region sandwiched between the upper surface of the conductive layer 112a2B and the lower surface of the conductive layer 112b2. Alternatively, the channel length L10_2B of transistor 10_2B may be defined as the thickness of the insulating layer 110b2. Or, the channel length L10_2B of transistor 10_2B may be defined as the depth of the opening 144B (here, this corresponds to the sum of the thickness of the insulating layer 110_2 on the conductive layer 112a2B and the thickness of the conductive layer 112b2). 【0136】 Here, the channel length L10_2B of transistor 10_2B is determined by the thickness of the insulating layer 110_2, the angle θ110_2 between the surface of the semiconductor layer 108_2B being formed within the opening 144B (here, the side surface of the insulating layer 110_2 and the side surface of the conductive layer 112b2) and the surface of the insulating layer 110_2 being formed (here, the upper surface of the conductive layer 112a2B), etc., and is not affected by the performance of the exposure apparatus used to fabricate the transistor. Therefore, the channel length can be set to a value smaller than the limiting resolution of the exposure apparatus, and a transistor of a very small size can be realized. 【0137】The channel length L10_2B can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L10_2B can also be 100 nm or more and 1 μm or less. By shortening the channel length L10_2B, the on-current of transistor 10_2B can be increased. 【0138】 The thickness of the insulating layer 110_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. 【0139】 The angle θ110_2 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less. The angle θ110_2 can also be 90 degrees. A smaller angle θ110_2 is preferable because it improves the coverage of the layer (semiconductor layer 108_2B, etc.) formed along the side wall of the opening 144B. On the other hand, a value of angle θ110_2 closer to 90 degrees is preferable because it reduces the area occupied by the transistor 10_2B on the substrate surface. 【0140】The channel width of transistor 10_2B is the length of the source region or the drain region in a plan view (Figure 1A). In other words, the channel width of transistor 10_2B is the length of the region where the semiconductor layer 108_2B and the conductive layer 112a2B are in contact, or the length of the region where the semiconductor layer 108_2B and the conductive layer 112b2 are in contact, in a plan view. Alternatively, the channel width of transistor 10_2B may be an intermediate value between the length of the region where the semiconductor layer 108_2B and the conductive layer 112a2B are in contact in a plan view and the length of the region where the semiconductor layer 108_2B and the conductive layer 112b2 are in contact, in a plan view. 【0141】 Here, the channel width of transistor 10_2B is described as the circumference of the region where the semiconductor layer 108_2B and the side surface of the conductive layer 112b2 on the side of the opening 144B are in contact. In Figure 1A, the channel width W10_2B of transistor 10_2B is shown by a solid double arrow. The channel width W10_2B can also be said to be the circumference of the opening 144B in a plan view. 【0142】 The channel width W10_2B is determined by the top surface shape of the aperture 144B, etc. The diameter of the aperture 144B refers to the shortest side of the smallest rectangle that circumscribes the aperture 144B in a plan view. When the aperture 144B is formed using photolithography, the diameter of the aperture 144B is greater than or equal to the limiting resolution of the exposure apparatus. This diameter is, for example, 0.20 μm or more and less than 5.0 μm. As shown in Figure 1A, if the top surface shape of the aperture 144B is circular, this diameter corresponds to the diameter of the aperture 144B, and the channel width W10_2B is the value obtained by multiplying this diameter by pi (π). 【0143】 The following describes the materials that can be used for each component of semiconductor devices. 【0144】[Semiconductor layer 108_1, semiconductor layer 108_2A, semiconductor layer 108_2B] The semiconductor materials that can be used for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B are not particularly limited. For example, elemental semiconductors or compound semiconductors can be used. For example, silicon or germanium can be used as elemental semiconductors. For example, gallium arsenide and silicon germanium can be used as compound semiconductors. For example, organic materials having semiconductor properties or metal oxides having semiconductor properties (also called oxide semiconductors) can be used as compound semiconductors. In addition, these semiconductor materials can also be configured to contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron). 【0145】 The crystallinity of the semiconductor material used in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B is not particularly limited, and any amorphous semiconductor or crystalline semiconductor (single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a crystalline semiconductor is preferable because it can suppress the degradation of transistor characteristics. 【0146】 Silicon can be used for each of the semiconductor layers 108_1, 108_2A, and 108_2B. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). 【0147】Transistors using amorphous silicon for semiconductor layers 108_1, 108_2A, and 108_2B can be formed on a large glass substrate and manufactured at low cost. Transistors using polycrystalline silicon for semiconductor layers 108_1, 108_2A, and 108_2B have high field-effect mobility and can operate at high speeds. Furthermore, transistors using microcrystalline silicon for semiconductor layers 108_1, 108_2A, and 108_2B have higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds. 【0148】 It is preferable that semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B each contain a metal oxide (oxide semiconductor) having semiconductor properties. Examples of metal oxides that can be used in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B include indium oxide, gallium oxide, and zinc oxide. It is preferable that the metal oxide contains at least indium (In) or zinc (Zn). It is also preferable that the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin. Element M is more preferably gallium. 【0149】Each of the semiconductor layers 108_1, 108_2A, and 108_2B contains, for example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also written as IWO), indium aluminum zinc oxide (In-Al-Zn oxide, IAZO), and Other materials that can be used include indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. Alternatively, silicon-containing indium tin oxides can be used. 【0150】 For the formation of metal oxides, sputtering or atomic layer deposition (ALD) can be suitably used. However, when forming metal oxides by sputtering, the atomic ratio of the target material may differ from that of the metal oxide. In particular, with zinc, the atomic ratio of the metal oxide may be lower than that of the target material. Specifically, it may be between 40% and 90% of the zinc content in the target material. 【0151】 When forming semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B by ALD, it is preferable to use a film deposition method such as thermal ALD or PEALD (Plasma Enhanced ALD). Thermal ALD is preferred because it exhibits extremely high step coverage. PEALD is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film deposition. 【0152】The metal oxide composition of semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B significantly affects the electrical characteristics and reliability of transistors 10_1, 10_2A, and 10_2B, respectively. 【0153】 For example, by increasing the indium content of the metal oxide, a transistor with a large on-current can be realized. Also, for example, by using a metal oxide that does not contain gallium or has a low gallium content in each of the semiconductor layers 108_1, 108_2A, and 108_2B, a transistor with high reliability against positive bias application can be made. Also, for example, by applying a metal oxide with a low content of element M to each of the semiconductor layers 108_1, 108_2A, and 108_2B, a transistor with high reliability against positive bias application can be made. Also, for example, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be made. 【0154】 Details regarding the metal oxide composition of semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B will be described later. 【0155】It is preferable to use a crystalline metal oxide layer for each of the semiconductor layers 108_1, 108_2A, and 108_2B. For example, metal oxide layers having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, etc., can be used. By using a crystalline metal oxide layer for semiconductor layers 108_1, 108_2A, and 108_2B, the defect level density in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B can be reduced, and a highly reliable transistor can be realized. The CAAC structure is a crystalline structure in which multiple nanocrystals (typically multiple IGZO nanocrystals) have c-axis orientation, and in the a-b plane, the multiple nanocrystals are linked without orientation. The CAAC structure allows for the realization of highly reliable transistors because the crystal grains are not as clearly visible in the a-b plane compared to the polycrystalline structure. 【0156】 The higher the crystallinity of the metal oxide layers used in semiconductor layers 108_1, 108_2A, and 108_2B, the lower the defect level density in semiconductor layers 108_1, 108_2A, and 108_2B, respectively. On the other hand, by using metal oxide layers with low crystallinity, it is possible to realize transistors that can conduct large currents. 【0157】The semiconductor layers 108_1, 108_2A, and 108_2B can each be a laminated structure of two or more metal oxide layers with different crystallinity. For example, a laminated structure can be formed of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, wherein the second metal oxide layer has regions with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have regions with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers in each of the semiconductor layers 108_1, 108_2A, and 108_2B can each have the same or approximately the same composition. By using a laminated structure of metal oxide layers with the same composition, for example, they can be formed using the same sputtering target, thus reducing manufacturing costs. For example, by using the same sputtering target and varying the ratio of the oxygen gas flow rate to the total film deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), a laminated structure of two or more metal oxide layers with different crystallinity can be formed. Furthermore, the two or more metal oxide layers in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B can each have different compositions. 【0158】 The thickness of each of the semiconductor layers 108_1, 108_2A, and 108_2B is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 10 nm to 70 nm, more preferably 15 nm to 70 nm, more preferably 15 nm to 50 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and more preferably 25 nm to 40 nm. 【0159】 Here, we will explain the oxygen vacancies that may be formed in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B. 【0160】As described above, when oxide semiconductors are used for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, creating oxygen vacancies in the oxide semiconductor. Furthermore, a defect called V can form when hydrogen is added to the oxygen vacancy. Ｏ H can function as a donor, generating electrons as carriers. Additionally, some hydrogen can combine with oxygen atoms bonded to metal atoms, also generating electrons. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics. Furthermore, because hydrogen in oxide semiconductors is easily affected by stresses such as heat and electric fields, a high hydrogen content in the oxide semiconductor may degrade the reliability of the transistor. 【0161】 V Ｏ H can function as a donor in oxide semiconductors. However, it is difficult to quantitatively evaluate such defects. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration assuming no electric field is applied may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration". 【0162】 Based on the above, when oxide semiconductors are used for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, the V in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B are as follows: Ｏ It is preferable to reduce H as much as possible to achieve high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain an oxide semiconductor with sufficiently reduced H, it is necessary to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration and dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to create oxygen vacancies (V Ｏ It is important to repair ). ＯBy using an oxide semiconductor with sufficiently reduced defects such as H in the channel formation region of a transistor, stable electrical characteristics can be imparted. Note that supplying oxygen to the oxide semiconductor to repair oxygen vacancies (V Ｏ ) may be referred to as an oxygen addition treatment. 【0163】 When an oxide semiconductor is used for each of the semiconductor layer 108_1, the semiconductor layer 108_2A, and the semiconductor layer 108_2B, the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is preferably 1×10 １８ cm −３ or less, more preferably less than 1×10 １７ cm −３ , even more preferably less than 1×10 １６ cm −３ , even more preferably less than 1×10 １３ cm −３ , even more preferably less than 1×10 １２ cm −３ . Note that there is no particular limitation on the lower limit value of the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region. For example, it can be 1×10 −９ cm −３ . 【0164】 A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has an extremely high field-effect mobility as compared with a transistor using amorphous silicon. Also, the OS transistor has a significantly small leakage current between the source and the drain in the off state (hereinafter also referred to as the off current), and can hold the charges accumulated in the capacitor connected in series with the transistor for a long period of time. Further, by applying the OS transistor to a semiconductor device, the power consumption of the semiconductor device can be reduced. 【0165】OS transistors can be applied to display devices. To increase the luminescence brightness of a light-emitting device included in the pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to silicon transistors (hereinafter referred to as Si transistors), OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied between the source and drain of an OS transistor. Therefore, by applying an OS transistor to the drive transistor of a pixel circuit, the amount of current flowing through the light-emitting device can be increased, and the luminescence brightness of the light-emitting device can be increased. 【0166】 When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thus allowing for precise control of the current flowing to the light-emitting device. This allows for an increase in the number of grayscale levels in the pixel circuit. 【0167】 In terms of the saturation characteristics of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting device, for example, even if there are variations in the current-voltage characteristics of the light-emitting device. In other words, when operating in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the luminescence brightness of the light-emitting device. 【0168】As described above, by using OS transistors in the drive transistors included in the pixel circuit, it is possible to achieve "suppression of black level floating," "increase in luminescence brightness," "multi-gradation," and "suppression of variations in light-emitting devices." 【0169】 OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays). 【0170】 [Insulating Layer] In a transistor according to one aspect of the present invention, and in a semiconductor device, display device, etc. to which a transistor according to one aspect of the present invention is applied, an inorganic insulating material or an organic insulating material can be used as the insulating layer (insulating layer 110_1, insulating layer 110_2, insulating layer 106_1, insulating layer 106_2, insulating layer 192, insulating layer 193, and insulating layer 194). Furthermore, a laminated structure of an inorganic insulating material and an organic insulating material can also be used as the insulating layer. 【0171】 As the inorganic insulating material, one or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used. 【0172】 In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content. The term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, silicon oxide-nitride refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride oxide refers to a material in which the nitrogen content is greater than the oxygen content. 【0173】For the analysis of oxygen and nitrogen content, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing elemental content, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods. 【0174】 Furthermore, for evaluating the film density of insulating layers, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR) can be used. Differences in film density can also sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Even when the same material is used for the insulating layer, differences in film density can sometimes be observed as differences in contrast at the boundaries between these densities in the cross-sectional TEM image. 【0175】The nitrogen content of an insulating layer can be confirmed, for example, by energy-dispersive X-ray spectroscopy (EDX). For example, when silicon nitride, silicon oxynitride, etc. are used for the insulating layer, the nitrogen content can be evaluated using the ratio of the peak height of nitrogen to the peak height of silicon. In EDX, the peak of a certain element refers to the point where the count number of that element reaches its maximum value in a spectrum where the energy of the characteristic X-ray is shown on the horizontal axis and the count number (detection value) of the characteristic X-ray is shown on the vertical axis. Alternatively, the count number at the characteristic X-ray energy specific to that element can be used, and the difference in nitrogen content can be confirmed by the ratio of the count number of nitrogen to the count number of silicon. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen. 【0176】 The hydrogen concentration in the insulating layer can be evaluated, for example, using SIMS. 【0177】 When hydrogen diffuses into semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, it reacts with oxygen atoms contained in the oxide semiconductor to form water, creating oxygen vacancies (V) in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, respectively. Ｏ ) may be formed. Furthermore, V Ｏ H is formed, and the carrier concentrations in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B may increase. By using a barrier insulating layer that suppresses hydrogen diffusion as an insulating layer in contact with each of semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, or as an insulating layer located around each of semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, oxygen vacancies (V) in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B can be reduced. Ｏ ) and V ＯThis allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. 【0178】 Oxygen deficiency (V) in the channel formation region of each transistor 10_1, transistor 10_2A, and transistor 10_2B Ｏ ) and V Ｏ H is preferably low. In particular, when the channel length is short, oxygen deficiency (V) in the channel formation region is preferable. Ｏ ) and V Ｏ The effect of H on the electrical characteristics and reliability of transistors 10_1, 10_2A, and 10_2B increases. For example, if V flows from the source region or drain region to the channel formation region... Ｏ When H diffuses, the carrier concentration in the channel formation region increases, which may cause fluctuations in the threshold voltages of transistors 10_1, 10_2A, and 10_2B, or a decrease in their reliability. Ｏ The effect of H diffusion on the electrical characteristics and reliability of transistors 10_1, 10_2A, and 10_2B increases as the channel length decreases. Semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, in particular, oxygen vacancies (V) in the channel formation region. Ｏ ) and V Ｏ By reducing H, it is possible to realize transistors with short channel lengths that have good electrical characteristics and high reliability. 【0179】 By using an oxygen-releasing insulating layer (for example, insulating layer 106_1, insulating layer 106_2, insulating layer 110b1, and insulating layer 110b2) in contact with each of the semiconductor layers 108_1, 108_2A, and 108_2B, oxygen can be supplied from the insulating layer to each of the semiconductor layers 108_1, 108_2A, and 108_2B. By supplying oxygen to the channel formation regions of each of the semiconductor layers 108_1, 108_2A, and 108_2B, oxygen vacancies (V) in semiconductor layers 108_1, 108_2A, and 108_2B can be reduced. Ｏ ) and VＯ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. Other methods for supplying oxygen to semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. 【0180】 It is preferable that insulating layers in contact with semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, or insulating layers located around semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, release little impurities (e.g., water and hydrogen) from themselves. The impurities referred to here are those that diffuse into semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, respectively, thereby creating oxygen vacancies (V) in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B. Ｏ ) and V Ｏ This refers to substances that can adversely affect the electrical characteristics of a transistor, such as by generating hydrogen (H). By reducing the release of impurities, the diffusion of these impurities into semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. 【0181】 In processes following the formation of semiconductor layers 108_1, 108_2A, and 108_2B, heat may be applied, causing oxygen to detach from each of these layers. However, oxygen is supplied to semiconductor layers 108_1, 108_2A, and 108_2B from the insulating layer in contact with each of these layers, thereby resolving oxygen deficiencies (V) in semiconductor layers 108_1, 108_2A, and 108_2B. Ｏ ) and V ＯThis method can suppress the increase in H. Furthermore, it allows for greater flexibility in the processing temperature during processes following the formation of semiconductor layers 108_1, 108_2A, and 108_2B. Specifically, the processing temperature can be increased during processes following the formation of semiconductor layers 108_1, 108_2A, and 108_2B. Therefore, it is possible to form transistors that exhibit good electrical characteristics and high reliability. 【0182】 [Insulating layer 110_1, insulating layer 110_2] Insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) can be made of inorganic insulating material or organic insulating material. Insulating layer 110_1 and insulating layer 110_2 can also be made of a laminated structure of inorganic insulating material and organic insulating material. 【0183】 Inorganic insulating materials can be suitably used as insulating layer 110_1 and insulating layer 110_2. One or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used as inorganic insulating materials. For example, one or more silicon oxide, silicon oxidized nitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride can be used as insulating layer 110_1 and insulating layer 110_2. 【0184】 The insulating layer 110_1 and insulating layer 110_2 can also be arranged in a laminated structure of two or more layers. In Figure 1B, etc., insulating layer 110_1 has a laminated structure of insulating layer 110a1, insulating layer 110b1 on insulating layer 110a1, and insulating layer 110c1 on insulating layer 110b1, and insulating layer 110_2 has a laminated structure of insulating layer 110a2, insulating layer 110b2 on insulating layer 110a2, and insulating layer 110c2 on insulating layer 110b2. Note that the insulating layers 110a1, 110b1, 110c1, 110a2, 110b2, and 110c2 can be made of the same material or different materials. 【0185】 It is preferable that insulating layers 110_1 and 110_2 release very little impurities (e.g., water and hydrogen) from themselves. 【0186】 The thickness of insulating layers 110b1 and 110b2 can be greater than the thickness of insulating layers 110a1 and 110a2, and the thickness of insulating layers 110c1 and 110c2. As described above, insulating layer 110b1 is an insulating layer that has oxygen to supply to semiconductor layer 108_1, and insulating layer 110b2 is an insulating layer that has oxygen to supply to semiconductor layer 108_2A and semiconductor layer 108_2B, respectively. Therefore, among the three insulating layers constituting insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and the three insulating layers constituting insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), by making the thickness of insulating layer 110b1 and insulating layer 110b2 the thickest, the amount of oxygen that can be contained in the entire insulating layer 110_1 and insulating layer 110_2 can be increased. It is preferable that the deposition rate of insulating layer 110b1 and insulating layer 110b2 is faster than the deposition rate of insulating layer 110a1 and insulating layer 110a2, and the deposition rate of insulating layer 110c1 and insulating layer 110c2. By increasing the deposition rate of thicker films, productivity can be increased. 【0187】 The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, each function as a barrier insulating layer that suppresses the detachment of gas (e.g., oxygen) from the insulating layer 110b1 and the insulating layer 110b2, respectively. It is preferable to use materials that do not easily allow gas to diffuse for the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, respectively. It is preferable that the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, each have regions with a higher film density than the insulating layer 110b1 and the insulating layer 110b2, respectively. By increasing the film density of the insulating layer, the barrier properties against gas can be improved. By slowing down the film deposition rate of the insulating layer, the film density can be increased, and the barrier properties against gas can be improved. 【0188】It is preferable to use oxides or oxidized nitrides as insulating layers 110b1 and 110b2. It is preferable to use films that release oxygen upon heating as insulating layers 110b1 and 110b2. For example, silicon oxide or silicon oxidized nitride can be suitably used as insulating layers 110b1 and 110b2. 【0189】 The insulating layers 110b1 and 110b2 release oxygen, allowing oxygen to be supplied from insulating layer 110b1 to semiconductor layer 108_1, and from insulating layer 110b2 to semiconductor layers 108_2A and 108_2B, respectively. It is preferable that insulating layers 110b1 and 110b2 have high oxygen diffusion coefficients. By increasing the oxygen diffusion coefficient, oxygen can diffuse more easily through insulating layer 110b1 and insulating layer 110b2, allowing oxygen to be efficiently supplied to semiconductor layers 108_1, 108_2A, and 108_2B, respectively. Furthermore, as described above, by making the thickness of insulating layer 110b1 and insulating layer 110b2 thicker than the thickness of insulating layer 110a1 and insulating layer 110c1, and insulating layer 110a2 and insulating layer 110c2, respectively, more oxygen can be supplied to semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B. 【0190】 The insulating layer 110_1 and insulating layer 110_2 are preferably formed by a film deposition method such as sputtering, ALD, or plasma CVD (PECVD: Plasma Enhanced Chemical Vapor Deposition). 【0191】In particular, by using the sputtering method and a film deposition method that does not use a hydrogen-containing gas as the deposition gas, it is possible to create a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B is suppressed, and the electrical characteristics of transistors 10_1, 10_2A, and 10_2B can be stabilized, respectively. When depositing silicon oxide by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing an oxygen-containing gas. Similarly, when depositing silicon nitride by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing a nitrogen-containing gas. Furthermore, when depositing aluminum oxide by sputtering, for example, the film can be deposited using an aluminum target in an atmosphere containing an oxidizing gas. 【0192】 Furthermore, silicon oxide and silicon nitride can be deposited using, for example, the PEALD method. Aluminum oxide and hafnium oxide can also be deposited using, for example, the thermal ALD method. By depositing an insulating layer using the PEALD method and the thermal ALD method, a dense insulating film can be formed, thereby improving barrier properties against oxygen and hydrogen. 【0193】 The insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, can be made of materials with a higher nitrogen content than insulating layers 110b1 and 110b2, respectively. By increasing the nitrogen content of the insulating layers, the barrier properties against oxygen and hydrogen can be enhanced. 【0194】 Furthermore, insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, may each have regions where the hydrogen concentration in the film is lower than that of insulating layer 110b1 and insulating layer 110b2, respectively. 【0195】It is preferable that insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, are impermeable to oxygen. Furthermore, it is preferable that insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, are impermeable to hydrogen. Insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, respectively, function as barrier insulating layers that suppress the diffusion of hydrogen from outside the transistor through insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2 to semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, respectively. Preferably, the film densities of insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, are higher than the film densities of insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve the barrier properties against oxygen and hydrogen. When silicon oxide or silicon oxide nitride is used for insulating layers 110b1 and 110b2, silicon nitride or silicon nitride oxide can be used for insulating layers 110a1, 110c1, 110a2, and 110c2. Furthermore, hafnium oxide or aluminum oxide can preferably be used as insulating layers 110a1, 110c1, 110a2, and 110c2. 【0196】 Furthermore, a structure can be used in which two or more layers selected from silicon nitride, silicon oxide nitride, hafnium oxide, and aluminum oxide are laminated as insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2. 【0197】If the oxygen contained in insulating layers 110b1 and 110b2 diffuses downward (towards the substrate 102), the amount of oxygen supplied from insulating layers 110b1 and 110b2 to semiconductor layers 108_1, 108_2A, and 108_2B may decrease. By providing insulating layers 110a1 and 110a2 below insulating layers 110b1 and 110b2, respectively, the diffusion of oxygen contained in insulating layers 110b1 and 110b2 downward can be suppressed. Furthermore, by providing insulating layers 110c1 and 110c2 on top of insulating layers 110b1 and 110b2, respectively, the diffusion of oxygen contained in insulating layers 110b1 and 110b2 upwards can be suppressed. Consequently, the amount of oxygen supplied from insulating layers 110b1 and 110b2 to semiconductor layers 108_1, 108_2A, and 108_2B increases, and the oxygen deficiencies (V) in semiconductor layers 108_1, 108_2A, and 108_2B are reduced. Ｏ ) and V Ｏ H can be reduced. 【0198】 Furthermore, by providing insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, the diffusion of hydrogen into semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B is suppressed, and oxygen vacancies (V) in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B are reduced. Ｏ ) and V Ｏ H can be reduced. 【0199】It is preferable that insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, each have a film thickness that functions as an oxygen and hydrogen barrier insulating layer. If the film thickness is too thin, the function as a barrier insulating layer may be reduced. On the other hand, if the film thickness is too thick, the region of semiconductor layer 108_1 in contact with insulating layer 110b1, and the regions of semiconductor layer 108_2A and semiconductor layer 108_2B in contact with insulating layer 110b2 become narrower, which may reduce the amount of oxygen supplied to semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, respectively. The film thickness of insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2 is preferably 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm, respectively. 【0200】 [Insulating layer 106_1, insulating layer 106_2] Insulating layers 106_1 and 106_2, which function as gate insulating layers, preferably have a low defect density. A low defect density in insulating layers 106_1 and 106_2 allows for the creation of a transistor with good electrical characteristics. Furthermore, insulating layers 106_1 and 106_2 preferably have a high dielectric breakdown voltage. A high dielectric breakdown voltage in insulating layers 106_1 and 106_2 allows for the creation of a highly reliable transistor. 【0201】 Furthermore, it is preferable that insulating layers 106_1 and 106_2 are insulating layers containing oxygen. It is also preferable that they are insulating layers that release oxygen upon heating. This allows, for example, when metal oxides are used for semiconductor layers 108_1, 108_2A, and 108_2B, the oxygen contained in insulating layers 106_1 and 106_2 to be supplied to each metal oxide. This allows oxygen deficiencies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of transistors 10_1, 10_2A, and 10_2B. 【0202】 For insulating layers 106_1 and 106_2, one or more insulating oxides, oxidized nitrides, nitride oxides, and nitrides can be used. For insulating layers 106_1 and 106_2, one or more silicon oxides, silicon oxidized nitrides, silicon nitrides, aluminum oxides, aluminum oxidized nitrides, aluminum nitrides, hafnium oxide, hafnium oxidized nitrides, gallium oxide, gallium oxidized nitrides, yttrium oxide, yttrium oxidized nitride, and Ga-Zn oxides can be used. Insulating layers 106_1 and 106_2 can be single layers or laminated layers. Insulating layers 106_1 and 106_2 can also have a laminated structure of oxides and nitrides, for example. 【0203】 In miniature transistors, if the thickness of the gate insulating layer becomes too thin, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium. 【0204】 It is preferable that insulating layers 106_1 and 106_2 release little impurities (e.g., water and hydrogen) from themselves. By reducing the release of impurities from insulating layers 106_1 and 106_2, the diffusion of these impurities into semiconductor layers 108_1, 108_2A, and 108_2B is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. 【0205】Since the insulating layer 106_1 is formed on the semiconductor layer 108_1 and the insulating layer 106_2 is formed on semiconductor layers 108_2A and 108_2B, it is preferable that the films be formed under conditions that minimize damage to each of the semiconductor layers 108_1, 108_2A, and 108_2B. For example, it is preferable to form them under conditions where the deposition rate (also called the deposition rate) is sufficiently slow. For example, when forming the insulating layer 106_1 and insulating layer 106_2 by plasma CVD, forming them under low power conditions can reduce the damage to each of the semiconductor layers 108_1, 108_2A, and 108_2B. 【0206】 Here, we will take as an example a configuration in which metal oxides are used for each of the semiconductor layers 108_1, 108_2A, and 108_2B, and explain the insulating layers 106_1 and 106_2 in detail. 【0207】 To improve the interfacial properties with semiconductor layers 108_1, 108_2A, and 108_2B, it is preferable to use one or more oxides and oxidized nitrides on at least the side of insulating layer 106_1 that contacts semiconductor layer 108_1, and on at least the side of insulating layer 106_2 that contacts semiconductor layers 108_2A and 108_2B, respectively. For insulating layers 106_1 and 106_2, for example, one or more silicon oxide and silicon oxidized nitride can be suitably used. Furthermore, it is even more preferable to use films that release oxygen upon heating for insulating layers 106_1 and 106_2. 【0208】Furthermore, insulating layers 106_1 and 106_2 can also be in a laminated structure. Insulating layer 106_1 can have a laminated structure consisting of an oxide film or oxynitride film on the side in contact with semiconductor layer 108_1 and a nitride film on the side in contact with conductive layer 104_1. Similarly, insulating layer 106_2 can have a laminated structure consisting of an oxide film or oxynitride film on the side in contact with semiconductor layers 108_2A and 108_2B and a nitride film on the side in contact with conductive layer 104_2. For example, silicon oxide and one or more silicon oxynitride films can be suitably used as the oxide film or oxynitride film. For example, silicon nitride can be suitably used as the nitride film. 【0209】 It is even more preferable that the film thickness of insulating layer 106_1 and insulating layer 106_2 be between 1 nm and 100 nm. It is preferable that insulating layer 106_1 and insulating layer 106_2 have regions with the above-mentioned film thickness in at least a portion of their respective areas. 【0210】 [Conductive layer 112a1, conductive layer 112b1, conductive layer 112a2A, conductive layer 112a2B, conductive layer 112b2] The conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2, which function as source and drain electrodes, can each be formed using one or more of the following: chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the aforementioned metals. For conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2, low-resistance conductive materials containing one or more of copper, silver, gold, or aluminum can be suitably used. Copper or aluminum are particularly preferred due to their excellent mass-productivity. 【0211】A metal oxide film (also called an oxide conductor) can be used for each of the conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2. Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide. 【0212】 Here, we will explain oxide conductors (OCs). For example, when an oxygen vacancy is formed in a metal oxide with semiconductor properties, and hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor. 【0213】 The conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2 can each be a laminated structure of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced. 【0214】 The conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2 can each be coated with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be performed by wet etching, thus reducing manufacturing costs. 【0215】 Furthermore, conductive layers 112a1 and 112b1 can be made of the same material or different materials. The same applies to conductive layers 112a2A and 112b2, and conductive layers 112a2B and 112b2. 【0216】Here, we will take as an example a configuration in which a metal oxide is used for each of the semiconductor layers 108_1, 108_2A, and 108_2B, and specifically explain the conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2. 【0217】 When oxide semiconductors are used for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, the oxygen contained in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B may oxidize conductive layer 112a1, conductive layer 112b1, conductive layer 112a2A, conductive layer 112a2B, and conductive layer 112b2, potentially increasing their resistance. The oxygen contained in insulating layer 110_1 and insulating layer 110_2 may oxidize conductive layer 112a1, conductive layer 112b1, conductive layer 112a2A, conductive layer 112a2B, and conductive layer 112b2, potentially increasing their resistance. 【0218】 Furthermore, the oxygen contained in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B oxidizes conductive layer 112a1, conductive layer 112b1, conductive layer 112a2A, conductive layer 112a2B, and conductive layer 112b2, thereby creating oxygen vacancies (V) in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, respectively. Ｏ In some cases, the amount of oxygen supplied from insulating layer 110_1 to semiconductor layer 108_1, and from insulating layer 110_2 to semiconductor layer 108_2A and semiconductor layer 108_2B may increase. Oxygen contained in insulating layer 110_1 and insulating layer 110_2 oxidizes conductive layer 112a1, conductive layer 112b1, conductive layer 112a2A, conductive layer 112a2B, and conductive layer 112b2, which may reduce the amount of oxygen supplied from insulating layer 110_1 to semiconductor layer 108_1, and from insulating layer 110_2 to semiconductor layer 108_2A and semiconductor layer 108_2B. 【0219】It is preferable to use materials that are resistant to oxidation for conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2. It is preferable to use oxide conductors for conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be suitably used. Nitride conductors can also be used for conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 112a1, conductive layer 112b1, conductive layer 112a2A, conductive layer 112a2B, and conductive layer 112b2 may each have a laminated structure of the aforementioned materials. 【0220】 By using materials that are resistant to oxidation for each of the conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2, it is possible to suppress oxidation caused by oxygen contained in semiconductor layers 108_1, 108_2A, and 108_2B, or oxygen contained in insulating layers 110_1 and 110_2, which would increase resistance. Furthermore, oxygen vacancies (V) in semiconductor layers 108_1, 108_2A, and 108_2B can be suppressed. Ｏ The increase in ) is suppressed, and the amount of oxygen supplied from the insulating layer 110_1 to the semiconductor layer 108_1, and from the insulating layer 110_2 to the semiconductor layer 108_2A and the semiconductor layer 108_2B can be increased. 【0221】[Conductive layer 104_1, conductive layer 104_2] The conductive layers 104_1 and 104_2, which function as gate electrodes, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or alloys comprising one or more of the aforementioned metals. Furthermore, the conductive layers 104_1 and 104_2 can also be made from materials that can be used for the conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2 described above. 【0222】 Although Figure 1B and other figures show conductive layers 104_1 and 104_2 as single-layer structures, this is not limited to this configuration. For example, conductive layers 104_1 and 104_2 can be arranged in a laminated structure of two or more layers. For instance, when conductive layers 104_1 and 104_2 are arranged in a two-layer laminated structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer 106_2 side, respectively) can be made of nitride or oxide, and the second conductive layer can be made of one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy composed of one or more of the aforementioned metals. Furthermore, for example, when conductive layer 104_1 and conductive layer 104_2 are arranged in a three-layer laminated structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer on the insulating layer 106_2 side, respectively) can be an alloy composed of one or more of the above-mentioned metals, or a nitride of said metal or alloy. The second conductive layer can be an alloy composed of one or more of the above-mentioned metals, and the third conductive layer can be an alloy composed of one or more of the above-mentioned metals, or a nitride of said metal or alloy. 【0223】[Insulating layer 192, insulating layer 194] It is preferable to use insulating materials that do not easily allow impurities to diffuse for the insulating layer 192 that covers transistor 10_1, and for the insulating layer 194 that is provided in the lower layer of transistors 10_2A and 10_2B. By providing insulating layers 192 and 194, it is possible to effectively suppress the diffusion of impurities from the outside into transistors 10_1, 10_2A, and 10_2B, and to improve the reliability of each of the transistors 10_1, 10_2A, and 10_2B. Examples of impurities include water and hydrogen. The insulating layer 192 and insulating layer 194 can each be an insulating layer having an inorganic insulating material or an insulating layer having an organic insulating material. It is preferable to use inorganic insulating materials for the insulating layer 192 and insulating layer 194. Specific examples of inorganic insulating materials that can be used for insulating layer 192 and insulating layer 194 include the inorganic insulating materials that can be used for insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2, respectively. For example, silicon nitride, silicon oxide nitride, hafnium oxide, aluminum oxide, etc., are preferably used for insulating layer 192 and insulating layer 194, respectively. 【0224】 [Insulating layer 193] The insulating layer 193, which fills the opening 143 and flattens the upper surface of the transistor 10_1, can be made of either an organic insulating material or an inorganic insulating material, or both. It is preferable to use an organic insulating material for the insulating layer 193. For example, by using an organic insulating material for the insulating layer 193, a film with excellent flatness can be easily formed at a relatively low temperature on a surface to be formed on that has steps. 【0225】Specific examples of organic insulating materials that can be used in the insulating layer 193 include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins. Photosensitive materials can also be used as organic insulating materials. Here, photosensitivity refers to the property of being sensitive to ultraviolet light, far ultraviolet light, electron beams, X-rays, etc. This property is used to form a resist pattern by exposure. For exposure of silicon-containing resists, ultraviolet light is mainly used, and more preferably far ultraviolet light. The raw material monomer used at this time may be aromatic, but in order to increase sensitivity, it is more desirable to have a structure that does not contain aromatic rings. For example, polyimide resin is preferably used for the insulating layer 193. 【0226】 Inorganic insulating materials can also be used for the insulating layer 193. Specific examples of inorganic insulating materials that can be used for the insulating layer 193 include the inorganic insulating materials that can be used for the insulating layer 110_1 and insulating layer 110_2, respectively. For example, silicon oxide, silicon oxide-nitride, silicon nitride, silicon oxide, silicon nitride, etc., are preferably used for the insulating layer 193. 【0227】 [Conductive layer 115] The conductive layer 115, which functions as a plug, can be made of a material that can be used for each of the aforementioned conductive layers 112a1, 112b1, 112a2A, 112a2B, and 112b2, or a material that can be used for each of the aforementioned conductive layers 104_1 and 104_2. 【0228】 Although Figure 1B and other figures show the conductive layer 115 as a single-layer structure, this is not limited to this, and it can also be a laminated structure of two or more layers. For example, when the conductive layer 115 is a two-layer laminated structure, the first conductive layer can be made of an oxidation-resistant material such as the aforementioned oxide conductor (e.g., ITO, ITSO, etc.) or nitride conductor (e.g., tantalum nitride, titanium nitride, etc.), and the second conductive layer can be made of a low-resistance conductive material containing one or more of copper, silver, gold, or aluminum. 【0229】In this case, it is preferable that the first conductive layer is provided in contact with the upper surface of the conductive layer 112b1, the side surface of the insulating layer 106_1, the side surface of the insulating layer 192, the side surface of the insulating layer 193, and the side surface of the insulating layer 194, respectively, within the openings 146 provided in the insulating layers 106_1, 192, 193, and 194, and that the second conductive layer is provided on the first conductive layer so as to fill the openings 146. This makes it possible to suppress, for example, the diffusion of oxygen contained in the semiconductor layer 108_1, etc., into the conductive layer 115, which would increase the resistance of the conductive layer 115. 【0230】 [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as the substrate 102. In addition, substrates on which semiconductor elements are provided can also be used as the substrate 102. The shape of the semiconductor substrate and insulating substrate can be circular or rectangular. 【0231】 A flexible substrate can be used as the substrate 102, and the semiconductor device 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the semiconductor device 100, etc. The release layer can be used to separate the semiconductor device from the substrate 102 after it has been partially or completely completed on it, and to transfer it to another substrate. In this case, the semiconductor device 100, etc., can be transferred to a substrate with poor heat resistance or to a flexible substrate. 【0232】 [Composition of metal oxides in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B] The composition of metal oxides in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B is described below. 【0233】The metal oxide composition of semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B significantly affects the electrical characteristics and reliability of transistors 10_1, 10_2A, and 10_2B, respectively. 【0234】 For example, by increasing the indium content of the metal oxide, it is possible to realize a transistor with a large on-current. 【0235】 When using In-Zn oxide for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, metal oxides with atomic ratios of metal elements of In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or close to these, can be used. 【0236】 When using In-Sn oxide for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin. For example, metal oxides with atomic ratios of metal elements of In:Sn = 1:1, In:Sn = 2:1, In:Sn = 3:1, In:Sn = 4:1, In:Sn = 5:1, In:Sn = 7:1, or In:Sn = 10:1, or close to these, can be used. 【0237】When In-M-Zn oxide is used for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, a metal oxide can be applied in which the atomic ratio of indium to the atomic number of metal elements is higher than the atomic ratio of element M. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, in semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, the atomic ratios of metal elements can be In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, and In:M:Zn=5 Metal oxides in the following ratios can be used: 1:8, In:M:Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or near these ratios. 【0238】 Furthermore, if element M contains multiple metallic elements, the sum of the atomic ratios of those metallic elements can be used as the atomic ratio of element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as elements M, the sum of the atomic ratios of gallium and aluminum can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as elements M, the sum of the atomic ratios of gallium and tin can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges. 【0239】It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of metal elements contained in the metal oxide is 30 atomic% to 100 atomic%, preferably 30 atomic% to 95 atomic%, more preferably 35 atomic% to 95 atomic%, more preferably 35 atomic% to 90 atomic%, more preferably 40 atomic% to 90 atomic%, more preferably 45 atomic% to 90 atomic%, more preferably 50 atomic% to 80 atomic%, more preferably 60 atomic% to 80 atomic%, and more preferably 70 atomic% to 80 atomic%. For example, when using In-Ga-Zn oxide for semiconductor layer 108_1, semiconductor layer 108_2A, and semiconductor layer 108_2B, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is within the above range. 【0240】 In this specification, the ratio of the number of indium atoms to the total number of atoms of the contained metal elements may be referred to as the indium content. The same applies to other metal elements. 【0241】 By increasing the indium content of the metal oxide, a transistor with a high on-current can be created. Applying this transistor to a transistor requiring a high on-current results in a semiconductor device with excellent electrical characteristics. 【0242】 For the analysis of the composition of metal oxides, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may not be detected. 【0243】 In this specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when describing an atomic ratio of In:M:Zn = 4:2:3 or a composition near that, it includes cases where the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Also, when describing an atomic ratio of In:M:Zn = 5:1:6 or a composition near that, it includes cases where the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when describing an atomic ratio of In:M:Zn = 1:1:1 or a composition near that, it includes cases where the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less. 【0244】 <Example of Semiconductor Device Configuration 2> Figures 2A and 2B show an example of the configuration of a semiconductor device 100A, which has a different configuration from the semiconductor device 100 shown in Figures 1A and 1B. Figure 2A shows a plan view of the semiconductor device 100A. Figure 2B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 2A. Figure 3B shows an equivalent circuit diagram of the semiconductor device 100A. 【0245】 The semiconductor device 100A includes transistor 10_1A, transistor 10_1B, transistor 10_2, insulating layer 110_1, insulating layer 110_2, insulating layer 192, insulating layer 193, insulating layer 194, and conductive layer 115. 【0246】Transistor 10_1A includes a conductive layer 104_1, an insulating layer 106_1, a semiconductor layer 108_1A, a conductive layer 112a1, and a conductive layer 112b1A. Conductive layer 104_1 functions as a gate electrode. Part of insulating layer 106_1 functions as a gate insulating layer. Conductive layer 112a1 functions as either a source electrode or a drain electrode. Conductive layer 112b1A functions as either a source electrode or a drain electrode. Of semiconductor layer 108_1A, the entire region that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode functions as a channel forming region. Furthermore, of semiconductor layer 108_1A, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region. 【0247】 The above explanation relating to transistor 10_1A can be applied to transistor 10_1B by replacing the conductive layer 104_1, insulating layer 106_1, semiconductor layer 108_1A, conductive layer 112a1, and conductive layer 112b1A with conductive layer 104_1, insulating layer 106_1, semiconductor layer 108_1B, conductive layer 112a1, and conductive layer 112b1B, respectively. 【0248】 Similarly, the above explanation relating to transistor 10_1A can be applied to transistor 10_2 by replacing the conductive layer 104_1, insulating layer 106_1, semiconductor layer 108_1A, conductive layer 112a1, and conductive layer 112b1A with conductive layer 104_2, insulating layer 106_2, semiconductor layer 108_2, conductive layer 112a2, and conductive layer 112b2, respectively. 【0249】 The semiconductor device 100A differs from the semiconductor device 100 mainly in that, of the three transistors it has, two transistors (transistor 10_1A and transistor 10_1B) that are connected in series are provided on the substrate 102, and the remaining transistor (transistor 10_2) is provided on top of these two transistors. 【0250】As shown in Figures 1B and 3A, in the semiconductor device 100, the conductive layer 112b2 functions as the other source electrode or drain electrode of transistor 10_2A, and also functions as the other source electrode or drain electrode of transistor 10_2B. In addition, the insulating layer 106_2 functions as the gate insulating layer of transistor 10_2A, and also functions as the gate insulating layer of transistor 10_2B. Furthermore, the conductive layer 104_2 functions as the gate electrode of transistor 10_2A, and also functions as the gate electrode of transistor 10_2B. 【0251】 Furthermore, in the semiconductor device 100, the conductive layer 115 has regions that are in contact with the upper surface of the conductive layer 112b1 and the lower surface of the conductive layer 112a2A, respectively. 【0252】 In other words, the semiconductor device 100 has a configuration in which transistors 10_2A and 10_2B are connected in series with each other. Another transistor (transistor 10_1) in the semiconductor device 100 is provided in a lower layer than transistors 10_2A and 10_2B, and has a configuration in which the other of the source electrode or drain electrode of transistor 10_1 (conductive layer 112b1) is connected to the other of the source electrode or drain electrode of transistor 10_2A (conductive layer 112a2A). 【0253】 In contrast, as shown in Figures 2B and 3B, in semiconductor device 100A, the conductive layer 112a1 functions as either the source electrode or the drain electrode of transistor 10_1A, and also functions as either the source electrode or the drain electrode of transistor 10_1B. Furthermore, the insulating layer 106_1 functions as both the gate insulating layer of transistor 10_1A and the gate insulating layer of transistor 10_1B. Furthermore, the conductive layer 104_1 functions as both the gate electrode of transistor 10_1A and the gate electrode of transistor 10_1B. 【0254】 Furthermore, in the semiconductor device 100A, the conductive layer 115 has regions that are in contact with the upper surface of the conductive layer 112b1A and the lower surface of the conductive layer 112a2, respectively. 【0255】 In other words, the semiconductor device 100A has a configuration in which transistors 10_1A and 10_1B are connected in series with each other. Another transistor (transistor 10_2) in the semiconductor device 100A is provided on a layer above transistors 10_1A and 10_1B, and has a configuration in which one of the source electrode or drain electrode of transistor 10_2 (conductive layer 112a2) is connected to the other of the source electrode or drain electrode of transistor 10_1A (conductive layer 112b1A). 【0256】 Therefore, it can be said that transistors 10_1A, 10_1B, and 10_2 in semiconductor device 100A correspond to transistors 10_2A, 10_2B, and 10_1 in semiconductor device 100, respectively. 【0257】 As shown in Figures 3A and 3B, semiconductor device 100 and semiconductor device 100A can be said to be equivalent in terms of their overall circuit configuration. That is, both semiconductor devices have the same configuration in which two of the three transistors are connected in series, and one of the source or drain electrodes of one of the transistors is connected to the other of the source or drain electrode of the remaining transistor. 【0258】 Thus, in one aspect of the present invention, if the overall circuit configuration of the semiconductor device is the same, the arrangement of the three transistors in the semiconductor device, the connection relationships between each conductive layer, and so on can be varied in various ways. This increases the degree of freedom in the layout, such as the routing of wiring connected to the semiconductor device. 【0259】 Furthermore, among the components of the semiconductor device 100A, the conductive layer 112b1A and the conductive layer 112b1B can each be made of the same material that can be used for the conductive layer 112b1 in the semiconductor device 100. Also, among the components of the semiconductor device 100A, the conductive layer 112a2 can each be made of the same material that can be used for the conductive layer 112a2A and the conductive layer 112a2B in the semiconductor device 100. 【0260】 Regarding semiconductor device 100A, other than the points mentioned above, you can refer to the content described for semiconductor device 100. 【0261】 <Example of semiconductor device configuration 3> Figure 4A shows an example of the configuration of semiconductor device 100B, which has a different configuration from semiconductor device 100 shown in Figure 1B. Figure 4A is a cross-sectional view of semiconductor device 100B corresponding to the dashed line A1-A2 in the plan view of semiconductor device 100 shown in Figure 1A. Figure 4B shows the equivalent circuit diagram of semiconductor device 100B. 【0262】 The semiconductor device 100B includes transistor 10_1, transistor 10_2A, transistor 10_2B, insulating layer 110_1, insulating layer 110_2, insulating layer 192, insulating layer 193, insulating layer 194, and conductive layer 115. 【0263】 For details of the configurations of transistors 10_1, 10_2A, and 10_2B, please refer to the information provided for semiconductor device 100 above. 【0264】 The semiconductor device 100A differs from the semiconductor device 100 mainly in the configuration of the conductive layer 115 connecting transistor 10_1 and transistor 10_2A. 【0265】 As shown in Figures 4A and 4B, in the semiconductor device 100B, the conductive layer 115 is provided so as to fill the openings 145 provided in the insulating layers 110_1, 106_1, 192, 193, and 194. The conductive layer 115 also has regions that are in contact with the upper surface of the conductive layer 112a1 and the lower surface of the conductive layer 112a2A. 【0266】 In other words, semiconductor device 100B has a configuration in which one of the source electrode or drain electrode of transistor 10_1 (conductive layer 112a1) is connected to one of the source electrode or drain electrode of transistor 10_2A (conductive layer 112a2A). 【0267】As shown in Figures 3A and 4B, semiconductor device 100 and semiconductor device 100B can be considered equivalent in terms of their overall circuit configuration. Thus, in one aspect of the present invention, the configuration of semiconductor device 100B can also be applied. This increases the degree of freedom in manufacturing semiconductor devices without being limited to the configuration of semiconductor device 100. 【0268】 Regarding semiconductor device 100B, other than the points mentioned above, you can refer to the content described for semiconductor device 100. 【0269】 <Example of semiconductor device configuration 4> Figure 5A shows an example of the configuration of a semiconductor device 100C, which has a different configuration from the semiconductor device 100 shown in Figure 1B. Figure 5A is a cross-sectional view of the semiconductor device 100C, corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100 shown in Figure 1A. Figure 5B shows the equivalent circuit diagram of the semiconductor device 100C. 【0270】 The semiconductor device 100C includes a transistor 10_1, a transistor 10_2A, a transistor 10_2B, an insulating layer 110_1, an insulating layer 110_2, an insulating layer 192, an insulating layer 193, an insulating layer 194, and a conductive layer 115. 【0271】 The semiconductor device 100C differs from the semiconductor device 100 mainly in the configuration of transistors 10_2A and 10_2B, as well as in the configuration of the conductive layer 115 connecting transistors 10_1 and 10_2A. 【0272】 As shown in Figures 5A and 5B, in semiconductor device 100C, one of the source electrodes or drain electrodes of transistors 10_2A and 10_2B is shared by the conductive layer 112a2. On the other hand, the other of the source electrodes or drain electrodes of transistors 10_2A and 10_2B is independent, with conductive layer 112b2A used for transistor 10_2A and conductive layer 112b2B used for transistor 10_2B. 【0273】Furthermore, in semiconductor device 100C, the conductive layer 115 is provided so as to fill the openings 155 provided in the insulating layers 106_1, 192, 193, 194, and 110_2. The conductive layer 115 also has regions that are in contact with the upper surface of the conductive layer 112b1 and the lower surface of the conductive layer 112b2A. 【0274】 In other words, semiconductor device 100C has a configuration in which the other side of the source electrode or drain electrode of transistor 10_1 (conductive layer 112b1) is connected to the other side of the source electrode or drain electrode of transistor 10_2A (conductive layer 112b2A). 【0275】 As shown in Figures 3A and 5B, semiconductor device 100 and semiconductor device 100C can be considered equivalent in terms of their overall circuit configuration. Thus, in one aspect of the present invention, the configuration of semiconductor device 100C can also be applied. This increases the degree of freedom in manufacturing semiconductor devices without being limited to the configuration of semiconductor device 100. 【0276】 Regarding semiconductor device 100C, other than the points mentioned above, you can refer to the content described for semiconductor device 100. 【0277】 <Example of semiconductor device configuration 5> Figure 6A shows an example of the configuration of semiconductor device 100D, which has a different configuration from semiconductor device 100C shown in Figure 5A. Figure 6A is a cross-sectional view of semiconductor device 100D, corresponding to the dashed line A1-A2 in the plan view of semiconductor device 100 shown in Figure 1A. Figure 6B shows the equivalent circuit diagram of semiconductor device 100D. 【0278】 The semiconductor device 100D includes a transistor 10_1, a transistor 10_2A, a transistor 10_2B, an insulating layer 110_1, an insulating layer 110_2, an insulating layer 192, an insulating layer 193, an insulating layer 194, and a conductive layer 115. 【0279】 For details on the configurations of transistors 10_1, 10_2A, and 10_2B, please refer to the information described in the semiconductor device 100C above. 【0280】The semiconductor device 100D differs from the semiconductor device 100C mainly in the configuration of the conductive layer 115 connecting transistor 10_1 and transistor 10_2A. 【0281】 As shown in Figures 6A and 6B, in the semiconductor device 100D, the conductive layer 115 is provided so as to fill the openings 157 provided in the insulating layers 110_1, 106_1, 192, 193, 194, and 110_2. The conductive layer 115 also has regions that are in contact with the upper surface of the conductive layer 112a1 and the lower surface of the conductive layer 112b2A. 【0282】 In other words, semiconductor device 100D has a configuration in which one of the source electrode or drain electrode of transistor 10_1 (conductive layer 112a1) is connected to the other of the source electrode or drain electrode of transistor 10_2A (conductive layer 112b2A). 【0283】 As shown in Figures 3A and 6B, semiconductor device 100 and semiconductor device 100D can be considered equivalent in terms of their overall circuit configuration. Thus, in one aspect of the present invention, the configuration of semiconductor device 100D can also be applied. This increases the degree of freedom in manufacturing semiconductor devices without being limited to the configuration of semiconductor device 100. 【0284】 Regarding semiconductor device 100D, other than the points mentioned above, you can refer to the content described in semiconductor device 100C. 【0285】 <Semiconductor Device Configuration Example 6> Figure 7A shows an example of the configuration of a semiconductor device 100E, which has a different configuration from the semiconductor device 100A shown in Figure 2B. Figure 7A is a cross-sectional view of the semiconductor device 100E, corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100A shown in Figure 2A. Figure 7B shows the equivalent circuit diagram of the semiconductor device 100E. 【0286】 The semiconductor device 100E includes transistor 10_1A, transistor 10_1B, transistor 10_2, insulating layer 110_1, insulating layer 110_2, insulating layer 192, insulating layer 193, insulating layer 194, and conductive layer 115. 【0287】The semiconductor device 100E differs from the semiconductor device 100A mainly in the configuration of transistors 10_1A and 10_1B, as well as in the configuration of the conductive layer 115 connecting transistors 10_1A and 10_2. 【0288】 As shown in Figures 7A and 7B, in the semiconductor device 100E, the source electrode or drain electrode of transistor 10_1A and transistor 10_1B is shared by the conductive layer 112b1. On the other hand, the source electrode or drain electrode of transistor 10_1A and transistor 10_1B are independent of each other, with conductive layer 112a1A used for transistor 10_1A and conductive layer 112a1B used for transistor 10_1B. 【0289】 Furthermore, in the semiconductor device 100E, the conductive layer 115 is provided so as to fill the openings 147 provided in the insulating layers 110_1, 106_1, 192, 193, and 194. The conductive layer 115 also has regions that are in contact with the upper surface of the conductive layer 112a1A and the lower surface of the conductive layer 112a2, respectively. 【0290】 In other words, the semiconductor device 100E has a configuration in which one of the source electrode or drain electrode of transistor 10_1A (conductive layer 112a1A) is connected to one of the source electrode or drain electrode of transistor 10_2 (conductive layer 112a2). 【0291】 As shown in Figures 3B and 7B, semiconductor device 100A and semiconductor device 100E can be considered equivalent in terms of their overall circuit configuration. Thus, in one aspect of the present invention, the configuration of semiconductor device 100E can also be applied. This increases the degree of freedom in manufacturing semiconductor devices without being limited to the configuration of semiconductor device 100A. 【0292】 Regarding semiconductor device 100E, other than the points mentioned above, you can refer to the content described in semiconductor device 100A. 【0293】<Example of semiconductor device configuration 7> Figure 8A shows an example of the configuration of a semiconductor device 100F, which has a different configuration from the semiconductor device 100A shown in Figure 2A. Figure 8A is a cross-sectional view of the semiconductor device 100F, corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100A shown in Figure 2A. Figure 8B shows the equivalent circuit diagram of the semiconductor device 100F. 【0294】 The semiconductor device 100F includes transistor 10_1A, transistor 10_1B, transistor 10_2, insulating layer 110_1, insulating layer 110_2, insulating layer 192, insulating layer 193, insulating layer 194, and conductive layer 115. 【0295】 For details on the configurations of transistors 10_1A, 10_1B, and 10_2, please refer to the information provided for semiconductor device 100A above. 【0296】 The semiconductor device 100F differs from the semiconductor device 100A mainly in the configuration of the conductive layer 115 connecting transistor 10_1A and transistor 10_2. 【0297】 As shown in Figures 8A and 8B, in the semiconductor device 100F, the conductive layer 115 is provided so as to fill the openings 155 provided in the insulating layers 106_1, 192, 193, 194, and 110_2. The conductive layer 115 also has regions that are in contact with the upper surface of the conductive layer 112b1A and the lower surface of the conductive layer 112b2, respectively. 【0298】 In other words, the semiconductor device 100F has a configuration in which the other side of the source electrode or drain electrode of transistor 10_1A (conductive layer 112b1A) is connected to the other side of the source electrode or drain electrode of transistor 10_2 (conductive layer 112b2). 【0299】 As shown in Figures 3B and 8B, semiconductor device 100A and semiconductor device 100F can be considered equivalent in terms of their overall circuit configuration. Thus, in one aspect of the present invention, the configuration of semiconductor device 100F can also be applied. This increases the degree of freedom in manufacturing semiconductor devices, without being limited to the configuration of semiconductor device 100A. 【0300】 Regarding semiconductor device 100F, other than the points mentioned above, you can refer to the content described in semiconductor device 100A. 【0301】 <Example of semiconductor device configuration 8> Figure 9A shows an example of the configuration of a semiconductor device 100G, which has a different configuration from the semiconductor device 100E shown in Figure 7A. Figure 9A is a cross-sectional view of the semiconductor device 100G, corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100A shown in Figure 2A. Figure 9B shows the equivalent circuit diagram of the semiconductor device 100G. 【0302】 The semiconductor device 100G includes transistor 10_1A, transistor 10_1B, transistor 10_2, insulating layer 110_1, insulating layer 110_2, insulating layer 192, insulating layer 193, insulating layer 194, and conductive layer 115. 【0303】 The semiconductor device 100G differs from the semiconductor device 100E mainly in the configuration of the conductive layer 115 connecting transistor 10_1A and transistor 10_2. 【0304】 As shown in Figures 9A and 9B, in the semiconductor device 100G, the conductive layer 115 is provided so as to fill the openings 157 provided in the insulating layers 110_1, 106_1, 192, 193, 194, and 110_2. The conductive layer 115 also has regions that are in contact with the upper surface of the conductive layer 112a1A and the lower surface of the conductive layer 112b2, respectively. 【0305】 In other words, the semiconductor device 100G has a configuration in which one of the source electrode or drain electrode of transistor 10_1A (conductive layer 112a1A) is connected to the other of the source electrode or drain electrode of transistor 10_2 (conductive layer 112b2). 【0306】 As shown in Figures 7B and 9B, semiconductor device 100E and semiconductor device 100G can be considered equivalent in terms of their overall circuit configuration. Thus, in one aspect of the present invention, the configuration of semiconductor device 100G can also be applied. This increases the degree of freedom in manufacturing semiconductor devices without being limited to the configuration of semiconductor device 100A. 【0307】 Regarding semiconductor device 100G, other than the points mentioned above, you can refer to the content described in semiconductor device 100E. 【0308】 <Example of semiconductor device configuration 9> Figure 10A shows an example of the configuration of a semiconductor device 100H, which has a different configuration from the semiconductor device 100 shown in Figure 1B. Figure 10A is a cross-sectional view of the semiconductor device 100H, corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100 shown in Figure 1A. Figure 10B shows the equivalent circuit diagram of the semiconductor device 100H. 【0309】 The semiconductor device 100H includes a transistor 10_1, a transistor 10_2A, a transistor 10_2B, an insulating layer 110_1, an insulating layer 110_2, an insulating layer 192, an insulating layer 193, an insulating layer 194, and a conductive layer 115. 【0310】 For details of the configurations of transistors 10_1, 10_2A, and 10_2B, please refer to the information provided for semiconductor device 100 above. 【0311】 The semiconductor device 100H differs from the semiconductor device 100 mainly in the transistor connected to transistor 10_1. 【0312】 As shown in Figure 10A, in the semiconductor device 100H, the conductive layer 112b1 extends beyond the semiconductor device 100 towards A2, and the conductive layer 112b1 and the conductive layer 112a2B are connected via the conductive layer 115. The conductive layer 115 is provided to fill the openings 146 provided in the insulating layers 106_1, 192, 193, and 194 in the region overlapping with the conductive layer 112b1 and the conductive layer 112a2B, and has regions in contact with the upper surface of the conductive layer 112b1 and the lower surface of the conductive layer 112a2B, respectively. 【0313】 In other words, semiconductor device 100H has a configuration in which the source electrode or drain electrode of transistor 10_1 (conductive layer 112b1) is connected to the source electrode or drain electrode of transistor 10_2B (conductive layer 112a2B). 【0314】As shown in Figures 3A and 10B, semiconductor device 100 and semiconductor device 100H can be considered equivalent in terms of their overall circuit configuration. Thus, in one aspect of the present invention, the configuration of semiconductor device 100H can also be applied. This increases the degree of freedom in manufacturing semiconductor devices without being limited to the configuration of semiconductor device 100. 【0315】 Regarding semiconductor device 100H, other than the points mentioned above, you can refer to the content described for semiconductor device 100. 【0316】 <Example of semiconductor device configuration 10> Figure 11A shows an example of the configuration of a semiconductor device 100I, which has a different configuration from the semiconductor device 100A shown in Figure 2B. Figure 11A is a cross-sectional view of the semiconductor device 100I, corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100A shown in Figure 2A. Figure 11B shows the equivalent circuit diagram of the semiconductor device 100I. 【0317】 The semiconductor device 100I includes transistor 10_1A, transistor 10_1B, transistor 10_2, insulating layer 110_1, insulating layer 110_2, insulating layer 192, insulating layer 193, insulating layer 194, and conductive layer 115. 【0318】 For details on the configurations of transistors 10_1A, 10_1B, and 10_2, please refer to the information provided for semiconductor device 100A above. 【0319】 The semiconductor device 100I differs from the semiconductor device 100A mainly in the transistor connected to transistor 10_2. 【0320】 As shown in Figure 11A, in the semiconductor device 100I, the conductive layer 112a2 extends beyond the semiconductor device 100A towards A2, and the conductive layer 112b1B and the conductive layer 112a2 are connected via the conductive layer 115. The conductive layer 115 is provided to fill the openings 146 provided in the insulating layers 106_1, 192, 193, and 194 in the region overlapping with the conductive layer 112b1B and the conductive layer 112a2, and has regions that are in contact with the upper surface of the conductive layer 112b1B and the lower surface of the conductive layer 112a2, respectively. 【0321】 In other words, the semiconductor device 100I has a configuration in which the source electrode or drain electrode of transistor 10_1B (conductive layer 112b1B) is connected to the source electrode or drain electrode of transistor 10_2 (conductive layer 112a2). 【0322】 As shown in Figures 3B and 11B, semiconductor device 100A and semiconductor device 100I can be considered equivalent in terms of their overall circuit configurations. Thus, in one aspect of the present invention, the configuration of semiconductor device 100I can also be applied. This increases the degree of freedom in manufacturing semiconductor devices, without being limited to the configuration of semiconductor device 100A. 【0323】 Regarding semiconductor device 100I, other than the points mentioned above, you can refer to the content described in semiconductor device 100A. 【0324】 <Example of semiconductor device configuration 11> Figure 12A shows an example of a semiconductor device configuration different from the semiconductor device 100 shown in Figure 1B. In Figure 12A, only the first layer transistor of the semiconductor device (shown here as transistor 10_1C) is extracted and shown in an enlarged view. 【0325】 The transistor 10_1C differs from the transistor 10_1 shown in Figure 1B, etc., mainly in that it has a conductive layer 114_1 that functions as a second gate electrode (also called a back gate electrode) and an insulating layer 110s1 that functions as a second gate insulating layer (also called a back gate insulating layer), and that the insulating layer 110_1 is composed of six layers: insulating layer 110d1, insulating layer 110e1, insulating layer 110f1, insulating layer 110g1, insulating layer 110h1, and insulating layer 110i1. 【0326】In transistor 10_1C, the insulating layer 110_1 is composed of six layers: conductive layer 112a1, insulating layer 110d1 on substrate 102, insulating layer 110e1 on insulating layer 110d1, insulating layer 110f1 on insulating layer 110e1, insulating layer 110g1 on insulating layer 110f1, insulating layer 110h1 on insulating layer 110g1, and insulating layer 110i1 on insulating layer 110h1. A conductive layer 114_1 is provided between insulating layer 110f1 and insulating layer 110g1. The conductive layer 112a1, insulating layer 110d1, insulating layer 110e1, insulating layer 110f1, conductive layer 114_1, insulating layer 110g1, insulating layer 110h1, insulating layer 110i1, and insulating layer 112b1 have regions that overlap each other. 【0327】 In transistor 10_1C, the opening 143 that reaches the conductive layer 112a1 is provided in the insulating layer 110d1, insulating layer 110e1, insulating layer 110f1, conductive layer 114_1, insulating layer 110g1, insulating layer 110h1, insulating layer 110i1, and insulating layer 112b1. 【0328】 Within the opening 143, an insulating layer 110s1 is provided in contact with a part of the upper surface of the conductive layer 112a1, the side surface of the insulating layer 110d1, the side surface of the insulating layer 110e1, the side surface of the insulating layer 110f1, the side surface of the conductive layer 114_1, the side surface of the insulating layer 110g1, the side surface of the insulating layer 110h1, the side surface of the insulating layer 110i1, and the side surface of the conductive layer 112b1. The upper end of the insulating layer 110s1 has a curved shape. 【0329】 A semiconductor layer 108_1 is provided in contact with another portion of the upper surface of the conductive layer 112a1 within the opening 143, the upper surface of the insulating layer 110s1 within the opening 143 (here, the surface facing the side wall of the opening 143), the curved portion of the insulating layer 110s1, and the upper surface of the conductive layer 112b1. 【0330】In transistor 10_1C, one surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 104_1 via insulating layer 106_1, and the other surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 114_1 via insulating layer 110s1. As described above, the conductive layer 114_1 functions as the second gate electrode of transistor 10_1C. The insulating layer 110s1 also functions as the second gate insulating layer of transistor 10_1C. 【0331】 The transistor 10_1C has two gate electrodes positioned on either side of the semiconductor layer 108_1, allowing a gate field to be applied to the carriers in the channel formation region from both sides of the semiconductor layer 108_1. Therefore, it can achieve a larger on-current than transistors 10_1 and others that have only one gate electrode (conductive layer 104_1). It can also achieve a smaller off-current. Furthermore, the threshold voltage can be shifted to the normally off side. In addition, the saturation characteristics of the current flowing when operating in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with increasing drain voltage). 【0332】 The insulating layer 110s1, which functions as the second gate insulating layer of transistor 10_1C, is preferably formed from a material that contains oxygen and releases oxygen through heat treatment or the like. For example, the insulating layer 110s1 can be made from the same material that can be used for the insulating layers 110b1 and 110b2 mentioned above. This allows, for example, when a metal oxide is used for the semiconductor layer 108_1, to supply oxygen from the insulating layer 110s1 to the metal oxide. This repairs oxygen deficiencies in the metal oxide, thereby improving the electrical characteristics and reliability of transistor 10_1C. 【0333】 The conductive layer 114_1, which functions as the second gate electrode of transistor 10_1C, can be made from the same material that can be used for the conductive layers 104_1 and 104_2 described above. 【0334】Of the six insulating layers constituting the insulating layer 110_1, insulating layer 110d1, insulating layer 110f1, insulating layer 110g1, and insulating layer 110i1 can be made from materials that can be used for insulating layers 110a1, 110c1, 110a2, and 110c2 as described above. In addition, insulating layer 110e1 and insulating layer 110h1 can be made from materials that can be used for insulating layers 110b1 and 110b2 as described above. 【0335】 As a result, for example, when a metal oxide is used for the semiconductor layer 108_1, oxygen present in the insulating layers 110e1 and 110h1 can be supplied to the semiconductor layer 108_1 via the insulating layer 110s1. This allows for the repair of oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 10_1C. Furthermore, it is possible to suppress the diffusion of oxygen present in the insulating layer 110e1 to the conductive layer 112a1 side via the insulating layer 110d1 and to the conductive layer 114_1 side via the insulating layer 110f1. Similarly, it is possible to suppress the diffusion of oxygen present in the insulating layer 110h1 to the conductive layer 114_1 side via the insulating layer 110g1 and to the conductive layer 112b1 side via the insulating layer 110i1. 【0336】 Furthermore, a transistor having a configuration similar to transistor 10_1C (i.e., a transistor having a second gate electrode and a second gate insulating layer) can be applied to any one or more of the three transistors in a semiconductor device according to one aspect of the present invention. 【0337】 Regarding transistor 10_1C, other than the points mentioned above, you can refer to the explanation given for transistor 10_1, etc. 【0338】 <Semiconductor Device Configuration Example 12> Figure 12B shows a transistor configuration example different from transistor 10_1C shown in Figure 12A. Note that in Figure 12B, only the first layer transistor of the semiconductor device (shown here as transistor 10_1D) is extracted and shown in an enlarged view. 【0339】Transistor 10_1D differs from transistor 10_1C shown in Figure 12A mainly in that it has an insulating layer 116 that covers the conductive layer 114_1 and functions as a barrier insulating layer for oxygen and hydrogen, and that the insulating layer 110_1 is composed of three layers: insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1. In addition, the shape of the insulating layer 110a1 differs from that of transistor 10_1 shown in Figure 1B, etc. 【0340】 In transistor 10_1D, the end of the insulating layer 110a1 on the side of the opening 143 has a shape that protrudes more than the side of the insulating layer 110b1 on the side of the opening 143, the side of the insulating layer 110c1 on the side of the opening 143, and the side of the conductive layer 112b1 on the side of the opening 143. 【0341】 Furthermore, a conductive layer 114_1 is provided on the insulating layer 110a1 so as to overlap with the insulating layer 110b1, insulating layer 110c1, and conductive layer 112b1. An insulating layer 116 is provided in contact with the upper surface and side surface of the conductive layer 114_1. An insulating layer 110s1 is provided in contact with the upper surface of the insulating layer 110a1 within the opening 143, the upper surface of the insulating layer 116 on the opening 143 side (here, the surface facing the side surface of the conductive layer 114_1), the side surface of the insulating layer 110b1 on the opening 143 side, the side surface of the insulating layer 110c1 on the opening 143 side, and the side surface of the conductive layer 112b1 on the opening 143 side. The upper end of the insulating layer 110s1 has a curved shape. 【0342】 Unlike transistor 10_1C, transistor 10_1D has a configuration in which the insulating layer 110s1 does not come into contact with the conductive layer 112a1. Therefore, it is possible to suppress problems such as a decrease in the on-current of transistor 10_1D caused by oxygen in the insulating layer 110s1 diffusing to the conductive layer 112a1 side and causing the conductive layer 112a1 to oxidize and increase its resistance. 【0343】 A semiconductor layer 108_1 is provided in contact with the upper surface of the conductive layer 112a1 within the opening 143, the side surface of the insulating layer 110a1 on the opening 143 side, the upper surface of the insulating layer 110s1 on the opening 143 side (here, the surface facing the side wall of the opening 143), the curved portion of the insulating layer 110s1, and the upper surface of the conductive layer 112b1. 【0344】 In transistor 10_1D, one surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 104_1 via insulating layer 106_1, and the other surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 114_1 via insulating layer 110s1 and insulating layer 116. As described above, conductive layer 114_1 functions as a second gate electrode. Insulating layer 110s1 also functions as a second gate insulating layer. Insulating layer 116 in the region sandwiched between conductive layer 114_1 and insulating layer 110s1 can also function as a second gate insulating layer. 【0345】 The insulating layer 116 is preferably formed of a material that functions as a barrier insulating layer for oxygen and hydrogen. For example, the insulating layer 116 can be made of the same material that can be used for the insulating layers 110a1, 110c1, 110a2, and 110c2 mentioned above. By covering the top and sides of the conductive layer 114_1 with the insulating layer 116 made of the said material, as shown in Figure 12B, it is possible to suppress problems such as oxygen from the insulating layers 110s1 and 110b1 diffusing into the conductive layer 114_1, which would reduce the conductivity of the conductive layer 114_1. 【0346】Here, the insulating layer 116 can be formed by a film deposition method such as plasma CVD or sputtering, but for example, the insulating layer 116 covering the top and sides of the conductive layer 114_1 can also be formed by oxidizing the surface of the conductive layer 114_1 by plasma treatment in an oxygen atmosphere. In this case, since an insulating layer 116 having the same function as the insulating layer 110a1 and insulating layer 110c1 can be formed without using film deposition methods such as plasma CVD or sputtering, the number of times the above film deposition method is applied can be reduced, and productivity can be increased. For example, productivity can be increased compared to a transistor 10_1C having six insulating layers constituting the insulating layer 110_1. In this case, it is preferable to use a material that is easily oxidized by plasma treatment in an oxygen atmosphere for the conductive layer 114_1. For example, it is preferable to use aluminum. Also, in this case, the insulating layer 116 will be an insulating layer made of an oxide of the element contained in the conductive layer 114_1. For example, if aluminum is used as the material for the conductive layer 114_1, the insulating layer 116 will be aluminum oxide. 【0347】 Furthermore, a transistor having a configuration similar to transistor 10_1D (i.e., a transistor having a second gate electrode and a second gate insulating layer) can be applied to any one or more of the three transistors in a semiconductor device according to one aspect of the present invention. 【0348】 Regarding transistor 10_1D, other than the points mentioned above, you can refer to the content explained for transistor 10_1C. 【0349】In the above, one embodiment of the present invention has shown an example of a semiconductor device having three transistors, two of which are connected in series, but it is not limited to this. For example, one embodiment of the present invention can have four or more transistors, three or more of which are connected in series (i.e., one of the source electrodes or drain electrodes of each transistor is connected to each other, and the gate electrodes of each transistor are also connected). By having three or more transistors connected in series, the overall current saturation can be further improved compared to a configuration in which two transistors are connected in series. 【0350】 <Example of Semiconductor Device Manufacturing Method> Below, an example of a semiconductor device manufacturing method according to one aspect of the present invention will be described with reference to the drawings. Here, the semiconductor device 100 shown in Figures 1A and 1B will be used as an example. 【0351】 Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD). 【0352】 Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering. 【0353】CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD). 【0354】 Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices can become charged by receiving charge from the plasma. This accumulated charge can damage the wiring, electrodes, or components in the semiconductor device. In contrast, thermal CVD, which does not use plasma, avoids this plasma damage, resulting in a higher yield for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition. 【0355】 As ALD methods, thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used. 【0356】 CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate. 【0357】Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices. 【0358】 Furthermore, the ALD method allows for the deposition of films of any composition by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor. 【0359】 Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating. 【0360】 Thin films constituting semiconductor devices can be processed using methods such as photolithography. In addition, thin films can also be processed using nanoimprint lithography, sandblasting, and lift-off methods. Furthermore, island-like thin films can be directly formed using deposition methods that utilize shielding masks such as metal masks. 【0361】 Photolithography typically involves two main methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, followed by exposure and development, to process the thin film into the desired shape. 【0362】In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam. 【0363】 For etching thin films, methods such as dry etching, wet etching, or sandblasting can be used. 【0364】 For planarization of thin films, polishing methods such as the CMP method are typically suitable. Alternatively, a reflow method, which involves heat treatment of the conductive layer to fluidize it, can also be suitably used. Furthermore, a combination of the reflow method and the CMP method can be employed. 【0365】 Furthermore, a process can be used in which a planarization film is formed on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching (e.g., dry etching) on ​​the planarization film, or a process in which a planarization film and a photoresist are formed in this order on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching on the planarization film and the photoresist, thereby filling only the planarization film into the depressions and flattening the entire top surface (these processes are sometimes called etch-back processes). When using an etch-back process, high-temperature heating (e.g., around 800°C) like that used in reflow methods is not required, so there is no need to worry about damage to the device during fabrication caused by such heating. In addition, an etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process with the CMP method due to the effects of bending, etc. 【0366】Other thin film planarization processes include dry etching and plasma treatment. Polishing, dry etching, and plasma treatment can be performed multiple times, or in combination. When combining these processes, the order of the steps is not particularly limited and can be appropriately set according to the surface irregularities of the workpiece. 【0367】 To precisely process a thin film to a desired thickness, for example, the CMP method can be used. In this method, first, the thin film is polished at a constant processing speed until a portion of its upper surface is exposed. Then, by polishing at a slower processing speed until the thin film reaches the desired thickness, high-precision processing becomes possible. 【0368】 Methods for detecting the end point of polishing include optical methods that involve irradiating the surface of the workpiece with light and detecting changes in the reflected light, physical methods that involve detecting changes in the polishing resistance that the processing equipment receives from the workpiece, and methods that use changes in magnetic field lines caused by eddy currents generated when magnetic field lines are applied to the workpiece. 【0369】 After the upper surface of the thin film is exposed, the thickness of the thin film can be precisely controlled by performing a polishing process at a slow processing speed while monitoring its thickness using an optical method such as a laser interferometer. If necessary, the polishing process can be repeated multiple times until the thin film reaches the desired thickness. 【0370】 Figures 13A to 27B illustrate the method for manufacturing the semiconductor device 100. Figure (A) in each figure shows a plan view corresponding to Figure 1A. Figure (B) in each figure shows a cross-sectional view along the dashed line A1-A2 in the plan view shown in Figure 1A. 【0371】 First, a conductive film that will become the conductive layer 112a1 is formed on the substrate 102, and the conductive layer 112a1 is formed by removing a portion of the conductive film (Figures 13A and 13B). For example, sputtering can be used to form the conductive film. In addition, either or both of the wet etching method and the dry etching method can be used to process the conductive film. 【0372】Next, insulating films 110a1f, 110b1f, and 110c1f are formed on the conductive layer 112a1 and the substrate 102 in this order. 【0373】 For the insulating film 110a1f, any material that can be used for the insulating layer 110a1 described above can be used as appropriate. 【0374】 As the insulating film 110a1f, for example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be suitably used. 【0375】 Specifically, as the insulating film 110a1f, silicon nitride can be deposited using, for example, a sputtering method. Alternatively, silicon nitride can be deposited using, for example, a PEALD method. Alternatively, aluminum oxide can be deposited using, for example, a sputtering method. 【0376】 Furthermore, for example, a configuration in which aluminum oxide and silicon nitride are layered can be used. For instance, aluminum oxide deposited using the sputtering method and silicon nitride deposited using the PEALD method can be used in a layered configuration. 【0377】 The insulating film 110b1f can be made from any of the materials that can be used for the insulating layer 110b1 described above. 【0378】 For example, silicon oxide, silicon oxide, silicon nitride, and the like can be suitably used as the insulating film 110b1f. 【0379】 Specifically, as the insulating film 110b1f, silicon oxide can be deposited using, for example, a sputtering method. Alternatively, silicon oxide can be deposited using, for example, a PECVD method. Alternatively, silicon oxynitride can be deposited using, for example, a PECVD method. 【0380】 Furthermore, for example, silicon oxide deposited using the sputtering method and silicon oxide or silicon oxidnitride deposited using the PECVD method can be used in a layered configuration. 【0381】The insulating film 110b1f can also be subjected to heat treatment after it has been formed. By performing heat treatment, water and hydrogen can be removed from the surface and within the insulating film 110b1f. 【0382】 The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can also be used as the atmosphere containing nitrogen or oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a content of hydrogen, water, etc. kept to a minimum, it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110b1f as much as possible. For the heat treatment, for example, an oven or a rapid thermal annealing (RTA) device can be used. Using an RTA device can shorten the heat treatment time. 【0383】 After the above heat treatment, a step of supplying oxygen to the insulating film 110b1f can also be performed. For example, after the insulating film 110b1f is formed, a metal oxide layer can be formed on the insulating film 110b1f to supply oxygen to the insulating film 110b1f. Alternatively, the heat treatment can be performed after the formation of the metal oxide layer. By performing the heat treatment after the formation of the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b1f, and oxygen can be contained in the insulating film 110b1f. The oxygen supplied to the insulating film 110b1f is supplied to the semiconductor layer 108_1 in a later step, thereby eliminating oxygen vacancies (V) in the semiconductor layer 108_1. Ｏ ) and V Ｏ H can be reduced. 【0384】After forming the metal oxide layer, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating film 110b1f through the metal oxide layer. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As the plasma treatment, a device that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that convert gas into plasma using high-frequency power include plasma etching devices and plasma ashing devices. 【0385】 The metal oxide layer may be an insulating layer or a conductive layer. The metal oxide layer may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO). 【0386】 It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108_1 as the metal oxide layer. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108_1. This allows the metal oxide layer to be formed using the same sputtering target as the semiconductor layer 108_1, thereby reducing manufacturing costs. 【0387】 When using a metal oxide material containing indium and gallium in the metal oxide layer, a material with a higher gallium composition (content) than the semiconductor layer 108_1 can be used. By using a material with a higher gallium composition (content) in the metal oxide layer, the barrier properties against oxygen can be further enhanced. This is preferable because it can suppress the detachment of oxygen contained in the insulating film 110b1f to the outside. 【0388】 The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to form it by sputtering in an atmosphere containing oxygen. This allows for a suitable supply of oxygen to the insulating film 110b1f during the formation of the metal oxide layer. 【0389】Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer. 【0390】 The process of supplying oxygen to the insulating film 110b1f is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc., can be supplied to the insulating film 110b1f by ion doping, ion implantation, plasma treatment, etc. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110b1f, and then oxygen can be supplied to the insulating film 110b1f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used. 【0391】 For the insulating film 110c1f, any material that can be used for the insulating layer 110c1 described above can be used as appropriate. 【0392】 For materials and film formation methods that can be used for insulating film 110c1f, refer to the description of materials and film formation methods that can be used for insulating film 110a1f mentioned above. 【0393】 Next, a conductive film 112b1f is formed on the insulating film 110c1f (Figures 14A and 14B). The conductive film 112b1f can be made from any of the materials previously used for the conductive layer 112b1. Furthermore, for the formation of the conductive film 112b1f, for example, sputtering can be used. 【0394】 Next, a conductive layer 112b1e is formed by removing a portion of the conductive film 112b1f (Figures 15A and 15B). Either a wet etching method or a dry etching method, or both, can be used to form the conductive layer 112b1e. The conductive layer 112b1e is formed to have a region that overlaps with the conductive layer 112a1. 【0395】Next, a process is performed to remove a portion of each of the conductive layer 112b1e, insulating film 110c1f, insulating film 110b1f, and insulating film 110a1f to form an opening 143 that reaches the conductive layer 112a1. For example, a dry etching method can be suitably used for this process. This process forms the conductive layer 112b1, insulating layer 110c1, insulating layer 110b1, and insulating layer 110a1, each having an opening (Figures 16A and 16B). 【0396】 Next, a semiconductor film that will become the semiconductor layer 108_1 is formed in contact with the upper surface of the conductive layer 112a1 within the opening 143, the side surfaces of the insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) within the opening 143, the side surfaces of the conductive layer 112b1 within the opening 143, and the upper surface of the conductive layer 112b1. After that, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_1 (Figures 17A and 17B). The semiconductor layer 108_1 is provided so as to have a region that overlaps with the opening 143. In addition, the semiconductor layer 108_1 is provided so that its edges have a region that is in contact with the conductive layer 112b1. 【0397】 For the semiconductor film that will become the semiconductor layer 108_1, any material that can be used for the semiconductor layer 108_1 as described above can be used as appropriate. 【0398】 For example, sputtering can be used to form the semiconductor film that will become the semiconductor layer 108_1. For example, when a metal oxide is used for the semiconductor layer 108_1, it can be formed by sputtering using a metal oxide target. Using the sputtering method is preferable because it allows for the relatively easy formation of films with low hydrogen content. 【0399】 Furthermore, when a metal oxide is used for the semiconductor layer 108_1, it can also be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent. 【0400】For example, when forming an In-Ga-Zn oxide, three precursors, namely a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used. Alternatively, two precursors, namely a precursor containing indium and a precursor containing gallium and zinc, can also be used. 【0401】 As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)indium, cyclopentadienylindium, indium(III) chloride, etc. can be used. 【0402】 Further, as the precursor containing gallium, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)gallium, dimethylchlorogallium, diethylchlorogallium, etc. can be used. 【0403】 Further, as the precursor containing zinc, dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionato)zinc, zinc chloride, etc. can be used. 【0404】 As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used. 【0405】 As a method for controlling the composition of the obtained film, adjusting the flow rate ratio of the source gases, the time for flowing the source gases, the order of flowing the source gases, etc. can be mentioned. Also, by adjusting these, a film with a continuously changing composition can be formed. Further, it is also possible to continuously form films with different compositions. 【0406】 It is preferable to use the ALD method for forming the semiconductor film that becomes the semiconductor layer 108_1 because the semiconductor layer 108_1 can be formed with a uniform thickness on the side surface of the insulating layer 110_1. 【0407】After forming the semiconductor film that becomes the semiconductor layer 108_1, heat treatment can also be performed. By the heat treatment, water and hydrogen contained in the semiconductor film can be reduced, and oxygen can be supplied from the insulating layer 110_1 to the semiconductor film. Note that the heat treatment can also be performed after processing the semiconductor film. 【0408】 The substrate temperature (stage temperature) during the formation of the semiconductor layer 108_1 is preferably 25°C (room temperature) or higher and 200°C or lower, and more preferably room temperature or higher and 130°C or lower. By setting the substrate temperature within the above range, when using a large-area glass substrate, bending or distortion of the substrate can be suppressed. 【0409】 The higher the substrate temperature during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed. Also, the higher the oxygen flow ratio, the higher the crystallinity of the metal oxide layer that can be formed. 【0410】 Subsequently, an insulating layer 106_1 is formed covering the semiconductor layer 108_1, the conductive layer 112b1, and the insulating layer 110c1 (FIGS. 18A and 18B). The insulating layer 106_1 has regions that contact the upper surface and side surfaces of the semiconductor layer 108_1, the upper surface and side surfaces of the conductive layer 112b1, and the upper surface of the insulating layer 110c1. 【0411】 For the insulating layer 106_1, the materials described above can be appropriately used. 【0412】 For the formation of the insulating layer 106_1, for example, the ALD method can be used. By using the ALD method, the insulating layer 106_1 can be preferably formed with good coverage for the semiconductor layer 108_1 formed to cover the opening 143. Note that when the semiconductor layer 108_1 can be sufficiently covered, a method other than the ALD method can also be used for the formation of the insulating layer 106_1. For example, the PECVD method, the sputtering method, etc. can be used. Thereby, the film formation rate of the insulating layer 106_1 can be increased compared to the case of using the ALD method, and thus the productivity can be enhanced. 【0413】Next, a conductive film that will become the conductive layer 104_1 is formed on the insulating layer 106_1, and a portion of the conductive film is removed to form the conductive layer 104_1 (Figures 19A and 19B). For forming the conductive film, sputtering, CVD, molecular beam epitaxy (MBE), PLD, ALD, etc., can be used as appropriate. Here, it is preferable that the conductive film is formed in contact with the insulating layer 106_1 that faces the side surface of the insulating layer 110_1 within the opening 143. Therefore, it is preferable to use a formation method that has good covering or embedding properties for forming the conductive film, and it is more preferable to use the CVD method or ALD method. In addition, one or both of the wet etching method and the dry etching method can be used for processing the conductive film. The conductive layer 104_1 is formed to have a region that overlaps with the opening 143. 【0414】 This forms transistor 10_1. 【0415】 Next, an insulating layer 192 is formed on the conductive layer 104_1 and the insulating layer 106_1. The insulating layer 192 is provided in contact with the upper and side surfaces of the conductive layer 104_1 and the upper surface of the insulating layer 106_1. For forming the insulating layer 192, for example, the ALD method, the PECVD method, or the sputtering method can be used. 【0416】 Next, an insulating layer 193 is formed on the insulating layer 192. The insulating layer 193 is formed to fill the opening 143. Furthermore, the height of the upper surface of the insulating layer 193 is formed to be higher than the height of the upper surface in any region of the insulating layer 192. For example, when an organic insulating material such as polyimide resin is used as the insulating layer 193, an insulating layer 193 with a generally flat upper surface can be easily formed by a method such as spin coating. Alternatively, after forming the insulating film that will become the insulating layer 193, an insulating layer 193 with a generally flat upper surface can be formed by performing an etch-back treatment on the insulating film. 【0417】 Next, an insulating layer 194 is formed on the insulating layer 193 (Figures 20A and 20B). For forming the insulating layer 194, for example, the ALD method, PECVD method, sputtering method, etc., can be used. 【0418】 Next, openings 146 reaching the conductive layer 112b1 are formed in the insulating layer 106_1, insulating layer 192, insulating layer 193, and insulating layer 194, and the conductive layer 115 is formed to fill the openings 146 (Figures 21A and 21B). For example, after forming the openings 146, a conductive film that will become the conductive layer 115 is formed on the insulating layer 194 and the conductive layer 112b1 using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Next, the conductive film is processed using a CMP method, etch-back treatment, etc. until the upper surface of the insulating layer 194 is exposed, and the conductive layer 115 embedded in the openings 146 can be formed. 【0419】 Next, conductive films that will become conductive layers 112a2A and 112a2B are formed on the conductive layer 115 and the insulating layer 194, and conductive layers 112a2A and 112a2B are formed by removing a portion of the conductive film (Figures 22A and 22B). For example, sputtering can be used to form the conductive film. In addition, either or both of the wet etching method and the dry etching method can be used to process the conductive film. Conductive layer 112a2A is formed to have a region in contact with conductive layer 115. It is also preferable that conductive layer 112a2A is formed to have a region that overlaps with the opening 143. Conductive layer 112a2B is provided adjacent to conductive layer 112a2A in a region different from conductive layer 112a2A on the insulating layer 194. 【0420】 Next, insulating films 110a2f, 110b2f, 110c2f, and conductive film 112b2f are formed on the conductive layer 112a2A, the conductive layer 112a2B, and the insulating layer 194 in this order (Figures 23A and 23B). For materials and formation methods that can be used for insulating films 110a2f, 110b2f, 110c2f, and conductive film 112b2f, refer to the descriptions above for materials and formation methods that can be used for insulating films 110a1f, 110b1f, 110c1f, and conductive film 112b1f, respectively. 【0421】Next, a conductive layer 112b2e is formed by removing a portion of the conductive film 112b2f (Figures 24A and 24B). Either a wet etching method or a dry etching method, or both, can be used to form the conductive layer 112b2e. The conductive layer 112b2e is formed to have regions that overlap with the conductive layers 112a2A and 112a2B, respectively. 【0422】 Next, a process is performed to remove a portion of each of the conductive layer 112b2e, insulating film 110c2f, insulating film 110b2f, and insulating film 110a2f, thereby forming an opening 144A that reaches the conductive layer 112a2A and an opening 144B that reaches the conductive layer 112a2B. For example, a dry etching method can be suitably used for this process. This process forms the conductive layer 112b2, insulating layer 110c2, insulating layer 110b2, and insulating layer 110a2, each having an opening (Figures 25A and 25B). 【0423】 Next, a semiconductor film is formed in contact with the upper surface of the conductive layer 112a2A within the opening 144A, the side surfaces of the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) within the opening 144A, the side surfaces of the conductive layer 112b2 within the opening 144A, the upper surface of the conductive layer 112a2B within the opening 144B, the side surfaces of the insulating layer 110_2 within the opening 144B, the side surfaces of the conductive layer 112b2 within the opening 144B, and the upper surface of the conductive layer 112b2, which will become the semiconductor layer 108_2A and semiconductor layer 108_2B. After that, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_2A and semiconductor layer 108_2B (Figures 26A and 26B). The semiconductor layer 108_2A is provided such that it has an overlapping region with the opening 144A, and the semiconductor layer 108_2B is provided such that it has an overlapping region with the opening 144B. Furthermore, the semiconductor layer 108_2A and the semiconductor layer 108_2B are provided such that their edges have regions in contact with the conductive layer 112b2. 【0424】 Regarding materials, formation methods, etc. that can be used for the semiconductor films that will become semiconductor layer 108_2A and semiconductor layer 108_2B, refer to the description above regarding materials, formation methods, etc. that can be used for the semiconductor film that will become semiconductor layer 108_1. 【0425】 Next, an insulating layer 106_2 is formed by covering the semiconductor layer 108_2A, the semiconductor layer 108_2B, and the conductive layer 112b2 (Figures 27A and 27B). The insulating layer 106_2 has regions that are in contact with the top and side surfaces of the semiconductor layer 108_2A, the top and side surfaces of the semiconductor layer 108_2B, the top and side surfaces of the conductive layer 112b2, and the top surface of the insulating layer 110c2. For materials that can be used for the insulating layer 106_2, and for the formation method, etc., refer to the description of materials that can be used for the insulating layer 106_1 above. 【0426】 Next, a conductive film that will become the conductive layer 104_2 is formed on the insulating layer 106_2, and a portion of the conductive film is removed to form the conductive layer 104_2. For materials that can be used for the conductive film, forming methods, processing methods, etc., refer to the description above for materials that can be used for the conductive film that will become the conductive layer 104_1. The conductive layer 104_2 is formed to have regions that overlap with openings 144A and 144B, respectively. 【0427】 This forms transistors 10_2A and 10_2B. 【0428】 By following the above steps, the semiconductor device 100 can be manufactured (Figures 1A and 1B). 【0429】 This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate. 【0430】 (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention. 【0431】In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide. 【0432】 Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide. 【0433】 This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO. 【0434】 IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single-crystal indium oxide. 【0435】 The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s). 【0436】Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen. 【0437】 On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm. 【0438】 Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is especially preferable to use elements in which the oxide is conductive or semiconducting. 【0439】Since indium oxide is an oxide capable of valence electron control as described above, a region with a low carrier concentration can be used as the channel formation region of a transistor, and a region with a high carrier concentration can be used as the source region and drain region of the transistor. As a result, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be formed. Note that valence electron control in a transistor using silicon is generally known. On the other hand, valence electron control in a transistor using indium oxide is a novel technical idea that cannot usually be conceived. By using this technical idea, a transistor with high mobility, low off-current, normally-off characteristics, and high reliability can be realized. 【0440】 The indium oxide film preferably has crystallinity. In particular, the indium oxide film is preferably a polycrystalline film, more preferably a single crystal film. A single crystal film does not have grain boundaries (also referred to as grain boundaries). By using a single crystal film, carrier scattering at grain boundaries can be suppressed, and a transistor exhibiting high field-effect mobility can be realized. Further, excellent effects such as suppressing variations in transistor characteristics caused by the grain boundaries can be achieved. 【0441】 In addition, a polycrystalline film is preferable because it can reduce carrier scattering compared to a microcrystalline film or an amorphous film and exhibits high field-effect mobility. When using a polycrystalline film, it is preferable to use a film with as large grain size as possible and few grain boundaries. In a transistor to which a polycrystalline film is applied, when the channel formation region has no grain boundaries or no grain boundaries are observed, since the channel formation region is located within the single crystal region included in the polycrystalline film, it can be regarded as a transistor to which a single crystal film is applied. 【0442】 Note that the crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD: X-Ray Diffraction), TEM, or electron diffraction (ED: Electron Diffraction). Alternatively, analysis may be performed by combining a plurality of these methods. 【0443】Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film. 【0444】 The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode. 【0445】 Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities. 【0446】 Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low. 【0447】 By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm２ / (V·s) or more, more preferably 250 cm ２ / (V・s) or more is possible. 【0448】 One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films. 【0449】 Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability. 【0450】 Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules. 【0451】 Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Additionally, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors. 【0452】 It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film. 【0453】 One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant. 【0454】 The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less. 【0455】 Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate. 【0456】Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified forms. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO. 【0457】 This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. 【0458】 (Embodiment 3) A semiconductor device according to one aspect of the present invention can be applied to a display device, for example. In this embodiment, a circuit, layout, etc. applicable to the display device will be described. 【0459】 Figure 28 is a block diagram illustrating a display device 300 to which a semiconductor device according to one aspect of the present invention can be applied. The display device 300 has a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432. 【0460】 The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (where m is an integer of 1 or more) and n columns (where n is an integer of 1 or more). 【0461】 The display unit 435 corresponds, for example, to the display unit 168 in Figure 55 described in Embodiment 4, and the pixels 230 correspond, for example, to the sub-pixels 11R, 11G, 11B, and 210 in Figure 55 described in Embodiment 4. 【0462】In Figure 28, the pixel 230 in the 1st row and nth column is shown as pixel 230[1,n], the pixel 230 in the mth row and 1st column is shown as pixel 230[m,1], and the pixel 230 in the mth row and nth column is shown as pixel 230[m,n]. In addition, any pixel 230 included in the display unit 435 may be shown as pixel 230[r,s]. r is an integer between 1 and m, and s is an integer between 1 and n. 【0463】 The circuit included in the first drive circuit section 431 functions, for example, as a scan line drive circuit. The circuit included in the second drive circuit section 432 functions, for example, as a signal line drive circuit. It is also possible to provide some circuit at a position facing the first drive circuit section 431 across the display section 435. Similarly, it is possible to provide some circuit at a position facing the second drive circuit section 432 across the display section 435. The circuits included in the first drive circuit section 431 and the second drive circuit section 432 are collectively referred to as the peripheral drive circuit 433. 【0464】 The peripheral drive circuit 433 can utilize various circuits such as shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, multiplexer circuits, demultiplexer circuits, and logic circuits. A semiconductor device 100 according to one aspect of the present invention can be used in the peripheral drive circuit 433. Furthermore, the transistors in the peripheral drive circuit and the transistors included in the pixel 230 can be formed in the same process. 【0465】 Furthermore, the display device 300 has m wires 436, each arranged in roughly parallel directions and whose potential is controlled by a circuit included in the first drive circuit section 431, and n wires 437, each arranged in roughly parallel directions and whose potential is controlled by a circuit included in the second drive circuit section 432. 【0466】 Note that Figure 28 shows an example where wiring 436 and wiring 437 are connected to pixel 230. However, wiring 436 and wiring 437 are just examples, and the wiring connected to pixel 230 is not limited to wiring 436 and wiring 437. 【0467】<Example of Pixel Circuit Configuration> Figures 29A to 30C show an example of the configuration of a pixel 230. The pixel 230 has a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, or pixel circuit 51E) and a light-emitting element 61. 【0468】 The light-emitting element described in this embodiment refers to a self-emissive display element such as an organic EL element (also called an OLED (Organic LED)). The light-emitting element connected to the pixel circuit can be a self-emissive light-emitting element such as an LED, microLED, QLED (Quantum-dot LED), or semiconductor laser. 【0469】 The pixel circuit 51A shown in Figure 29A is a 3Tr1C type pixel circuit having transistors 52A, 52B, 52C, and a capacitor 53. 【0470】 One of the sources or drains of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL. The other source or drain of transistor 52A is connected to the gate of transistor 52B and one terminal of capacitor 53. One of the sources or drains of transistor 52B is connected to wiring ANO. The other source or drain of transistor 52B is connected to one of the sources or drains of transistor 52C, the other terminal of capacitor 53, and the anode of light-emitting element 61. The cathode of light-emitting element 61 is connected to wiring VCOM. The region where the other source or drain of transistor 52A, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND. The other source or drain of transistor 52C is connected to wiring V0. For example, a reference potential is supplied to wiring V0. The gate of transistor 52C is connected to wiring GL. 【0471】Wiring GL corresponds to wiring 436, and wiring SL corresponds to wiring 437. Wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61. Transistor 52A has the function of controlling the conduction state (a state in which current can flow) or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM. Transistor 52A can also be called a selection transistor because it functions as a switch for controlling the selection and deselection of the pixel 230. 【0472】 By turning transistor 52A ON, an image signal is supplied from wiring SL to node ND. Subsequently, by turning transistor 52A OFF, the image signal is held at node ND. To ensure reliable retention of the image signal supplied to node ND, it is preferable to use a transistor with low off-current for transistor 52A. For example, it is preferable to use an OS transistor as transistor 52A. 【0473】 Transistor 52B has the function of controlling the amount of current flowing to the light-emitting element 61. Transistor 52B can also be called a driving transistor. Capacitor 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting element 61 is controlled according to the image signal supplied to the gate (node ​​ND) of transistor 52B. 【0474】 Transistor 52C has the function of controlling the conduction or non-conduction state between the source or drain of transistor 52B and the wiring V0 based on the potential of the wiring GL. Wiring V0 is a wiring that provides a reference potential. When an n-channel transistor is used for transistor 52B, the reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source voltage of transistor 52B. 【0475】Furthermore, the wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside. 【0476】 For example, any of the semiconductor devices 100, 100B to 100D, and 100H shown in Embodiment 1 can be applied to the pixel circuit 51A. In this case, the combination of transistors 10_2A and 10_2B connected in series can be applied to transistor 52B as a single transistor. By applying the combination of transistors 10_2A and 10_2B connected in series to transistor 52B, which functions as a drive transistor, a drive transistor with better current saturation than a configuration with only one transistor can be obtained. Also, transistor 10_1 can be applied to transistor 52C. 【0477】 For example, any of the semiconductor devices 100A, 100E to 100G, and 100I shown in Embodiment 1 can be applied to the pixel circuit 51A. In this case, the combination of transistors 10_1A and 10_1B connected in series can be treated as a single transistor and applied to transistor 52B. Also, transistor 10_2 can be applied to transistor 52C. 【0478】 The pixel circuit 51B shown in Figure 29B is a configuration in which, in the pixel circuit 51A shown in Figure 29A, transistor 52B has a back gate, and the wiring connected to the gate of transistor 52A and the wiring connected to the gate of transistor 52C are independent of each other. 【0479】The back gate of transistor 52B is connected to the other source or drain of transistor 52B, one source or drain of transistor 52C, the other terminal of capacitor 53, and the anode of light-emitting element 61. By connecting the back gate of transistor 52B to the other source or drain of transistor 52B, the operation of transistor 52B can be made more stable. 【0480】 Furthermore, the gate of transistor 52A is connected to wiring GL1, and the gate of transistor 52C is connected to wiring GL2. Unlike the pixel circuit 51A shown in Figure 29A, by providing separate wiring for the gate of transistor 52A and wiring for the gate of transistor 52C, it is possible to apply different potentials to the gates of the two transistors, thereby allowing the two transistors to operate independently. 【0481】 For example, in any of the semiconductor devices 100, 100B to 100D, and 100H shown in Embodiment 1, a configuration in which one or both of transistors 10_2A and 10_2B are replaced with transistor 10_1C (see Figure 12A) or transistor 10_1D (see Figure 12B) can be applied to the pixel circuit 51B. In this case, the combination of two transistors connected in series (transistors provided on the upper layer side of the semiconductor device) can be treated as a single transistor and applied to transistor 52B. The remaining transistors (transistors provided on the lower layer side of the semiconductor device) can be applied to transistor 52C. 【0482】For example, in any of the semiconductor devices 100A, 100E to 100G, and 100I shown in Embodiment 1, a configuration in which one or both of transistors 10_1A and 10_1B are replaced with transistor 10_1C or transistor 10_1D can be applied to the pixel circuit 51B. In this case, a combination of two transistors connected in series (transistors provided on the lower layer side of the semiconductor device) can be treated as a single transistor and applied to transistor 52B. The remaining transistor (transistor provided on the upper layer side of the semiconductor device) can be applied to transistor 52C. 【0483】 In the pixel circuit 51B, only transistor 52B has a back gate, but this is not limited to this configuration. It is also possible to have one or more of transistors 52A to 52C have a back gate. 【0484】 The pixel circuit 51C shown in Figure 30A has a configuration in which a transistor 52D is added to the pixel circuit 51A shown in Figure 29A. The pixel circuit 51C shown in Figure 30A is a 4Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, and a capacitor 53. 【0485】 One of the sources or drains of transistor 52D is connected to node ND, and the other source or drain is connected to wiring V0. 【0486】 Wirings GL1, GL2, and GL3 are connected to the pixel circuit 51C. Wiring GL1 is connected to the gate of transistor 52A, wiring GL2 is connected to the gate of transistor 52C, and wiring GL3 is connected to the gate of transistor 52D. In this embodiment, wirings GL1, GL2, and GL3 are sometimes collectively referred to as wiring GL. Therefore, there may be more than one wiring GL. 【0487】By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods. 【0488】 The pixel circuit 51D shown in Figure 30B is an example of the pixel circuit 51C shown in Figure 30A with the addition of a capacitor 53A. The capacitor 53A functions as a retaining capacitor. The pixel circuit 51C shown in Figure 30A is a 4Tr1C type pixel circuit. The pixel circuit 51D shown in Figure 30B is a 4Tr2C type pixel circuit. 【0489】 For example, any of the semiconductor devices 100, 100B to 100D, and 100H shown in Embodiment 1 can be applied to pixel circuits 51C and 51D, respectively. In this case, the combination of transistors 10_2A and 10_2B connected in series can be treated as a single transistor and applied to transistor 52B. Also, transistor 10_1 can be applied to transistor 52C. 【0490】 For example, any of the semiconductor devices 100A, 100E to 100G, and 100I shown in Embodiment 1 can be applied to the pixel circuit 51C and the pixel circuit 51D, respectively. In this case, the combination of transistors 10_1A and 10_1B connected in series can be treated as a single transistor and applied to transistor 52B. Also, transistor 10_2 can be applied to transistor 52C. 【0491】 Although the pixel circuits 51C and 51D are configured so that neither transistor has a back gate, this is not limited to this configuration. It is also possible to have one or more of transistors 52A to 52D have a back gate. 【0492】The pixel circuit 51E shown in Figure 30C is a 6Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, 52E, 52F, and a capacitor 53. 【0493】 One source or drain of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL2. One source or drain of transistor 52D is connected to wiring ANO, and the gate of transistor 52D is connected to wiring GL1. The other source or drain of transistor 52D is connected to one source or drain of transistor 52B. The other source or drain of transistor 52B is connected to the other source or drain of transistor 52A, and to one source or drain of transistor 52F. The gate of transistor 52F is connected to wiring GL3. 【0494】 One source or drain of transistor 52E is connected to the other source or drain of transistor 52D, and one source or drain of transistor 52B. The other source or drain of transistor 52E is connected to the gate of transistor 52B and one terminal of capacitor 53. The other terminal of capacitor 53 is connected to the other source or drain of transistor 52F, the anode of light-emitting element 61, and one source or drain of transistor 52C. The gates of transistor 52E and transistor 52C are connected to wiring GL4. The other source or drain of transistor 52C is connected to wiring V0. The region to which the other source or drain of transistor 52E, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND. 【0495】For example, any of the semiconductor devices 100, 100B to 100D, and 100H shown in Embodiment 1 can be applied to the pixel circuit 51E. In this case, the combination of transistors 10_2A and 10_2B connected in series can be treated as a single transistor and applied to transistor 52B. Also, transistor 10_1 can be applied to any of transistors 52A, 52D, 52E, or 52F. 【0496】 For example, any of the semiconductor devices 100A, 100E to 100G, and 100I shown in Embodiment 1 can be applied to the pixel circuit 51E. In this case, the combination of transistors 10_1A and 10_1B connected in series can be treated as a single transistor and applied to transistor 52B. Also, transistor 10_2 can be applied to any of transistors 52A, 52D, 52E, or 52F. 【0497】 In the pixel circuit 51E, none of the transistors have back gates, but this is not limited to this configuration. One or more of the transistors 52A to 52F may have back gates. 【0498】 In the following, specific layout examples of the aforementioned pixel circuit and examples of its manufacturing method, to which a semiconductor device according to one aspect of the present invention can be applied, will be described with reference to Figures 31A to 54B. 【0499】In Figures 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, and 53, (A) and (B) respectively show an example of the layout of the pixel circuit 51C shown in Figure 30A (hereinafter, the layout of (A) in each of the above figures will be referred to as the first layout, and the layout of (B) in each of the above figures will be referred to as the second layout). Also, in Figures 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, and 54, (A) shows an example of the layout of the pixel circuit 51A shown in Figure 29A (hereinafter referred to as the third layout), and (B) shows an example of the layout of the pixel circuit 51E shown in Figure 30C (hereinafter referred to as the fourth layout). 【0500】 Each layout assumes that the transistors 52B, which function as drive transistors for pixel circuits 51A, 51C, and 51E respectively, are configured as two transistors connected in series (hereinafter referred to as transistors 52B1 and 52B2). 【0501】 Furthermore, in the following, the transistors (transistors 52A to 52D) in the pixel circuit 51C are assumed to be arranged in two layers, with transistors 52C and 52D in the first layer and transistors 52A and 52B in the second layer. Similarly, the transistors (transistors 52A to 52C) in the pixel circuit 51A are assumed to be arranged in two layers, with transistor 52B in the first layer and transistors 52A and 52C in the second layer. Similarly, the transistors (transistors 52A to 52F) in the pixel circuit 51E are assumed to be arranged in two layers, with transistors 52A, 52B, and 52F in the first layer and transistors 52C, 52D, and 52E in the second layer. 【0502】Furthermore, for the first and third layouts, the line and spacing of the patterns in each layer is formed with a design value of 1.5 μm, while for the second and fourth layouts, the line and spacing of the patterns in each layer is formed with a design value of 1.0 μm. 【0503】 First, a conductive layer 112a1 is formed (Figures 31A to 32B). For details on how to form the conductive layer 112a1, please refer to the description in Figures 13A and 13B in the <Example of Semiconductor Device Manufacturing Method>. 【0504】 Next, an insulating film (not shown) which will become the insulating layer 110_1, and a conductive layer which will become the conductive layer 112b1 are formed on the conductive layer 112a1 in this order. Then, the conductive layer is processed to form the conductive layer 112b1e (Figures 33A to 34B). For details on how to form the conductive layer 112b1e, etc., refer to the description in Figures 14A to 15B in <Examples of Semiconductor Device Manufacturing Methods>. 【0505】 Next, the insulating film that will become the insulating layer 110_1 and a portion of the conductive layer 112b1e are removed to form an opening 143 that reaches the conductive layer 112a1, and the insulating layer 110_1 (not shown) and the conductive layer 112b1 are formed (Figures 35A to 36B). For details on how to form the opening 143, etc., refer to the description in Figures 16A and 16B in <Example of Method for Manufacturing a Semiconductor Device>. 【0506】 Next, a semiconductor layer 108_1 is formed on the conductive layer 112b1 such that it has a region that overlaps with the opening 143 (Figures 37A to 38B). For details on how to form the semiconductor layer 108_1, please refer to the description in Figures 17A and 17B in the <Example of Semiconductor Device Manufacturing Method>. 【0507】Next, an insulating layer 106_1 (not shown) and a conductive film that will become the conductive layer 104_1 are formed on the semiconductor layer 108_1 in that order, and then the conductive film is processed to form the conductive layer 104_1 (Figures 39A to 40B). For information on how to form the conductive layer 104_1 and the like, refer to the description in Figures 18A to 19B in <Examples of Semiconductor Device Manufacturing Methods>. 【0508】 As a result, transistors 52C and 52D are formed in Figure 39A and Figure 39B, respectively. Transistors 52B1 and 52B2 are formed in Figure 40A, respectively. Transistors 52A, 52B1, 52B2, and 52F are formed in Figure 40B, respectively. The aforementioned transistors are transistors placed in the first layer of pixel circuit 51A, pixel circuit 51C, and pixel circuit 51E, respectively. 【0509】 Next, insulating layers 192, 193, and 194 (none of which are shown) are formed in this order on each transistor shown in Figures 39A to 40B. Then, an opening 146 is formed in the insulating layer in the region overlapping with the conductive layer 112b1. Next, a conductive layer 115 is formed to fill the opening 146 (Figures 41A to 42B). For information on how to form the conductive layer 115, etc., refer to the description in Figures 20A to 21B in <Examples of Semiconductor Device Manufacturing Methods>. 【0510】 The following steps concern the fabrication of the transistors located in the second layer of each of the pixel circuits 51A, 51C, and 51E. For clarity, only the components of the structures formed in the second layer will be illustrated below. 【0511】Next, a conductive layer 112a2 (corresponding to conductive layers 112a2A and 112a2B in the case of semiconductor device 100) is formed on the conductive layer 115 and the insulating layer 194 (Figures 43A to 44B). For details on how to form the conductive layer 112a2, refer to the description in Figures 22A and 22B in <Examples of Semiconductor Device Manufacturing Methods>. Figures 43A to 44A show an example in which a conductive layer 112a3 is formed using a separate mask after the conductive layer 112a2 has been formed. The conductive layer 112a3 is, for example, a conductive layer that becomes the wiring ANO in pixel circuit 51A and pixel circuit 51C, respectively. The conductive layer 112a3 can be formed using the same method as the wiring 112a2, using a material that can be used for the wiring 112a2. 【0512】 Next, an insulating film (not shown) which will become the insulating layer 110_2, and a conductive film which will become the conductive layer 112b2 are formed in this order on the conductive layer 112a2 (and on the conductive layer 112a3). Then, the conductive film is processed to form the conductive layer 112b2e (Figures 45A to 46B). For information on how to form the conductive layer 112b2e, etc., refer to the description in Figures 23A to 24B in <Examples of Semiconductor Device Manufacturing Methods>. 【0513】 Next, the insulating film that will become the insulating layer 110_2 and a portion of the conductive layer 112b2e are removed to form an opening 144 (in the case of the semiconductor device 100, an opening corresponding to openings 144A and 144B) that reaches the conductive layer 112a2 (and conductive layer 112a3), and the insulating layer 110_2 (not shown) and the conductive layer 112b2 are formed (Figures 47A to 48B). For information on how to form the opening 144, etc., refer to the description in Figures 25A and 25B in <Examples of Methods for Manufacturing Semiconductor Devices>. 【0514】 Next, a semiconductor layer 108_2 (corresponding to semiconductor layer 108_2A and semiconductor layer 108_2B in the case of semiconductor device 100) is formed on the conductive layer 112b2 such that it has a region that overlaps with the opening 144 (Figures 49A to 50B). For details on how to form the semiconductor layer 108_2, refer to the description in Figures 26A and 26B in <Examples of Methods for Manufacturing Semiconductor Devices>. 【0515】 Next, an insulating layer 106_2 (not shown) and a conductive film that will become the conductive layer 104_2 are formed on the semiconductor layer 108_2 in that order, and then the conductive film is processed to form the conductive layer 104_2 (Figures 51A to 52B). For information on how to form the conductive layer 104_2 and the like, refer to the description in Figures 27A and 27B in <Examples of Semiconductor Device Manufacturing Methods>. 【0516】 As a result, transistors 52A, 52B1, and 52B2 are formed in Figure 51A and Figure 51B, respectively. Also, in Figure 52A, transistors 52A and 52C are formed, respectively. Also, in Figure 52B, transistors 52C, 52D, and 52E are formed, respectively. The aforementioned transistors are transistors that are placed in the second layer of pixel circuit 51A, pixel circuit 51C, and pixel circuit 51E, respectively. 【0517】 Figure 53A shows a layout (first layout) in which the second layer of the pixel circuit 51C shown in Figure 51A is superimposed on the first layer of the pixel circuit 51C shown in Figure 39A. Figure 53B shows a layout (second layout) in which the second layer of the pixel circuit 51C shown in Figure 51B is superimposed on the first layer of the pixel circuit 51C shown in Figure 39B. Figure 54A shows a layout (third layout) in which the second layer of the pixel circuit 51A shown in Figure 52A is superimposed on the first layer of the pixel circuit 51A shown in Figure 40A. Figure 54B shows a layout (fourth layout) in which the second layer of the pixel circuit 51E shown in Figure 52B is superimposed on the first layer of the pixel circuit 51E shown in Figure 40B. 【0518】Figure 53A shows that, in the first layout, transistors 52A and 52D, and transistors 52B1 and 52C, among the transistors of the pixel circuit 51C (transistor 52A, transistor 52B (transistor 52B1 and transistor 52B2), transistor 52C, and transistor 52D), are superimposed on each other. For example, when semiconductor device 100 is applied to pixel circuit 51C, transistor 10_1 corresponds to transistor 52C, transistor 10_2A corresponds to transistor 52B1, and transistor 10_2B corresponds to transistor 52B2. 【0519】 Figure 53B shows that, in the second layout, transistors 52A and 52D, and transistors 52B1 and 52C, among the transistors of the pixel circuit 51C (transistor 52A, transistor 52B (transistor 52B1 and transistor 52B2), transistor 52C, and transistor 52D), are superimposed on each other. For example, when semiconductor device 100 is applied to pixel circuit 51C, transistor 10_1 corresponds to transistor 52C, transistor 10_2A corresponds to transistor 52B1, and transistor 10_2B corresponds to transistor 52B2. 【0520】 Figure 54A shows that, in the third layout, transistors 52A and 52B1 of the transistors (transistor 52A, transistor 52B (transistors 52B1 and 52B2), and transistor 52C) of the pixel circuit 51A are superimposed. It can also be seen that parts of transistors 52B2 and 52C are superimposed. For example, when semiconductor device 100A is applied to pixel circuit 51A, transistor 10_2 corresponds to transistor 52C, transistor 10_1A corresponds to transistor 52B2, and transistor 10_1B corresponds to transistor 52B1. 【0521】Figure 54B shows that, in the fourth layout, transistors 52A and 52C are superimposed on each other among the transistors (transistor 52A, transistor 52B (transistor 52B1 and transistor 52B2), transistor 52C, transistor 52D, transistor 52E, and transistor 52F) of the pixel circuit 51E. It can also be seen that parts of transistor 52B1 and transistor D, and parts of transistor 52B2 and transistor 52E are superimposed on each other. For example, when semiconductor device 100A is applied to pixel circuit 51E, transistor 10_2 corresponds to transistor 52D, transistor 10_1A corresponds to transistor 52B1, and transistor 10_1B corresponds to transistor 52B2. 【0522】 Furthermore, when the layout shown in Figure 53A (first layout) is applied to the pixel circuit 51C, a resolution of 2000 ppi or higher can be achieved. Also, when the layout shown in Figure 53B (second layout) is applied to the pixel circuit 51C, a resolution of 3000 ppi or higher can be achieved. Furthermore, when the layout shown in Figure 54A (third layout) is applied to the pixel circuit 51A, a resolution of 2000 ppi or higher can be achieved. Finally, when the layout shown in Figure 54B (fourth layout) is applied to the pixel circuit 51E, a resolution of 2400 ppi or higher can be achieved. 【0523】 As described above, by using a semiconductor device according to one embodiment of the present invention in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced. Therefore, the resolution of the display device can be increased. For example, a display device can be realized with a resolution of 1,000 ppi or more and 10,000 ppi or less, preferably 2,000 ppi or more and 9,000 ppi or less, more preferably 3,000 ppi or more and 8,000 ppi or less, even more preferably 4,000 ppi or more and 8,000 ppi or less, even more preferably 5,000 ppi or more and 8,000 ppi or less, and even more preferably 6,000 ppi or more and 8,000 ppi or less. 【0524】Furthermore, by reducing the area occupied by the pixel circuit, the number of pixels in the display device can be increased (higher resolution). For example, it becomes possible to realize display devices with extremely high resolutions such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels). 【0525】 Therefore, by using a semiconductor device according to one aspect of the present invention in the pixel circuit of a display device, the display quality of the display device can be improved. Furthermore, in a bottom-emission type display device using an EL element, the aperture ratio of the pixels can be increased. Pixels with a high aperture ratio can emit light with the same brightness as pixels with a low aperture ratio, but with a lower current density. Therefore, the reliability of the display device can be improved. 【0526】 The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. 【0527】 (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 55 to 59. 【0528】 The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices. 【0529】Furthermore, the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, and as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses. 【0530】 A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a Flexible Printed Circuit (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an Integrated Circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method. 【0531】 [Display device 50A] Figure 55 shows a perspective view of the display device 50A. 【0532】 The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 55, substrate 152 is shown with a dashed line. 【0533】 The display device 50A includes a display unit 168, a connection unit 140, a circuit unit 164, wiring 165, etc. Figure 55 shows an example in which IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 55 can also be described as a display module having the display device 50A, an IC, and an FPC. 【0534】The connection portion 140 is provided on the outside of the display unit 168. The connection portion 140 can be provided along one or more sides of the display unit 168. There may be one or more connection portions 140. Figure 55 shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit. The connection portion 140 connects the common electrode of the display element to the conductive layer, and can supply potential to the common electrode. 【0535】 The circuit section 164 includes, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 can be configured to include both a scan line drive circuit and a signal line drive circuit (also called a source driver). 【0536】 The wiring 165 has the function of supplying signals and power to the display unit 168 and the circuit unit 164. These signals and power are input to the wiring 165 from an external source via the FPC 172, or from the IC 173. 【0537】 Figure 55 shows an example in which IC 173 is provided on the substrate 151 using the COG method or COF method, etc. For example, IC 173 can be an IC having one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can also be configured without an IC. Alternatively, the IC can be mounted on the FPC using the COF method, etc. 【0538】 One embodiment of the present invention can be applied, for example, to one or both of the display unit 168 and the circuit unit 164 of a display device 50A. 【0539】 For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device. 【0540】 The display unit 168 is the area in the display device 50A that displays images, and has a plurality of periodically arranged pixels 210. Figure 55 shows an enlarged view of one pixel 210. 【0541】 There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements. 【0542】 The pixel 210 shown in Figure 55 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. 【0543】 Each sub-pixel 11R, sub-pixel 11G, and sub-pixel 11B includes a display element and a circuit that controls the driving of the display element. 【0544】 Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs using a light source and color conversion technology with quantum dot materials can also be used. 【0545】 Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices. 【0546】 Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs, OLEDs, and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs. 【0547】Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials). 【0548】 The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element. 【0549】 Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode. 【0550】 In this embodiment, the explanation will mainly be given using the case where a light-emitting element is used as the display element. 【0551】 Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides. 【0552】 Figure 56 shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 168, a portion of the connection section 140, and a portion of the end section. 【0553】 The display device 50A shown in Figure 56 has transistors 205D, 205R, 205G, 205B, 206R, 206G, 206B, light-emitting elements 130R, 130G, 130B, etc. between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light. 【0554】An insulating layer 197 is provided on the substrate 151. Transistors 205D, 205R, 205G, and 205B are provided on the insulating layer 197. 【0555】 It is preferable to use a material for the insulating layer 197 that does not easily absorb impurities such as water and hydrogen. This allows the insulating layer 197 to function as a barrier layer, effectively suppressing the diffusion of impurities from the substrate 151 to the transistor. Therefore, the reliability of the display device can be improved. 【0556】 The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability. 【0557】 Furthermore, the display device 50A is a top-emission type. In the top-emission type, transistors and the like can be arranged overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type. 【0558】 Transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. These transistors can be manufactured using the same materials and the same process. 【0559】In this embodiment, an example is shown in which OS transistors are used for transistors 205D, 205R, 205G, 205B, 206R, 206G, and 206B. For transistors 205D, 205R, 205G, and 205B, for example, transistors 10_2A or 10_2B in the semiconductor device 100 of one aspect of the present invention can be used. Alternatively, for example, transistors 10_1A or 10_1B in the semiconductor device 100A of one aspect of the present invention can be used. Furthermore, for transistors 206R, 206G, and 206B, for example, transistor 10_1 in the semiconductor device 100 of one aspect of the present invention can be used. Alternatively, for example, transistor 10_2 in the semiconductor device 100A of one aspect of the present invention can be used. 【0560】 For example, transistor 10_1 in semiconductor device 100 according to one aspect of the present invention can be used for transistor 205D. Alternatively, transistor 10_2 in semiconductor device 100A according to one aspect of the present invention can be used. 【0561】 In other words, the display device 50A can apply a semiconductor device according to one embodiment of the present invention to both the display unit 168 and the circuit unit 164. By using a semiconductor device according to one embodiment of the present invention (in Figure 56, etc., the semiconductor device 100A shown in Figures 2A and 2B is exemplified) in the display unit 168, the pixel size can be reduced, and higher resolution can be achieved. 【0562】 Furthermore, by using one of the transistors in the semiconductor device according to one embodiment of the present invention in the circuit section 164, the area occupied by the circuit section 164 can be reduced, and a narrow bezel can be achieved. For the semiconductor device according to one embodiment of the present invention, please refer to the description of the earlier embodiment. 【0563】In the cross-sectional view of the display device shown in Figure 56, only two of the three transistors (transistors 205R and 206R, transistors 205G and 206G, and transistors 205B and 206B) of the semiconductor device 100A used for each sub-pixel of the display unit 168 are shown. In Figure 56, each of transistors 206R, 206G, and 206B corresponds to transistor 10_2 of the semiconductor device 100A, and each of transistors 205R, 205G, and 205B corresponds to transistor 10_1A of the semiconductor device 100A. The transistor corresponding to transistor 10_1B of the semiconductor device 100A is located on the back side of each of transistors 205R, 205G, and 205B, and is not shown in the cross-sectional view of Figure 56. 【0564】 Transistors 205D, 205R, 205G, and 205B each have a conductive layer 104_1 that functions as a gate electrode, an insulating layer 106_1 that functions as a gate insulating layer, a conductive layer 112a1 that functions as one of the source electrode or drain electrode, a conductive layer 112b1A that functions as the other of the source electrode or drain electrode, and a semiconductor layer 108_1 having a metal oxide. 【0565】 Furthermore, transistors 206R, 206G, and 206B each have a conductive layer 104_2 that functions as a gate electrode, an insulating layer 106_2 that functions as a gate insulating layer, a conductive layer 112a2 that functions as one of the source electrode or drain electrode, a conductive layer 112b2 that functions as the other of the source electrode or drain electrode, and a semiconductor layer 108_2 having a metal oxide. 【0566】 Furthermore, the transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures. 【0567】The display device of this embodiment may have, for example, one or more of the following: planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be either top-gate or bottom-gate types. Alternatively, the device may have a configuration in which gates are provided above and below the semiconductor layer in which the channel is formed. 【0568】 Furthermore, the display device of this embodiment may also have a transistor (Si transistor) that uses silicon in the channel formation region. 【0569】 Examples of silicon include single-crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, it is preferable to use a transistor having an LTPS in the semiconductor layer (hereinafter also referred to as an LTPS transistor). LTPS transistors have high field-effect mobility and good frequency characteristics. 【0570】 The transistors in the circuit unit 164 and the transistors in the display unit 168 can have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 can all be the same or there can be two or more types. Similarly, the structures of the multiple transistors in the display unit 168 can all be the same or there can be two or more types. 【0571】 All of the transistors in the display unit 168 can be OS transistors, all of the transistors in the display unit 168 can be Si transistors, and some of the transistors in the display unit 168 can be OS transistors and the rest can be Si transistors. 【0572】For example, by using both an LTPS transistor and an OS transistor in the display unit 168, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for a transistor that functions as a switch to control conduction and non-conduction between wires, and an LTPS transistor is used for a transistor that controls current. 【0573】 For example, one of the transistors in the display unit 168 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. Either the source or the drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit. 【0574】 On the other hand, the other transistor in the display unit 168 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and either the source or the drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly reduced (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image. 【0575】 An insulating layer 195 is provided so as to cover transistors 206R, 206G, and 206B. 【0576】 The insulating layer 195 preferably functions as a protective layer for the transistor. Similar to the insulating layer 197, it is preferable to use a material for the insulating layer 195 that does not easily absorb impurities such as water and hydrogen. This allows the insulating layer 195 to function as a barrier insulating layer, effectively suppressing the diffusion of impurities from above the transistor into the transistor. 【0577】 In this way, by providing an insulating layer 197 below (on the substrate 151 side) transistors 205D, 205R, 205G, 205B, 206R, 206G, and 206B, and an insulating layer 195 above them, the transistors can be sandwiched between upper and lower barrier layers. This effectively suppresses the diffusion of impurities into the transistors from the outside, further improving the reliability of the display device. 【0578】 An insulating layer 235 is provided on the insulating layer 195. Preferably, the insulating layer 235 functions as a planarizing layer that fills in any steps or irregularities formed on the transistors 205R, 205G, and 205B, and flattens the upper surface. 【0579】 Furthermore, it is preferable that the outermost layer of the insulating layer 235 functions as an etching protection layer. This makes it possible to suppress the formation of recesses in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, the insulating layer 235 can be configured to have recesses that are formed during processing of the pixel electrodes 111R, 111G, 111B, etc. 【0580】 A light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B are provided on the insulating layer 235. 【0581】 The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 135 on the EL layer 113R. The light-emitting element 130R shown in Figure 56 emits red light (R). The EL layer 113R has a light-emitting layer that emits red light. 【0582】 The light-emitting element 130G has a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 135 on the EL layer 113G. The light-emitting element 130G shown in Figure 56 emits green light (G). The EL layer 113G has a light-emitting layer that emits green light. 【0583】The light-emitting element 130B has a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 135 on the EL layer 113B. The light-emitting element 130B shown in Figure 56 emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light. 【0584】 In Figure 56, EL layers 113R, 113G, and 113B are all shown with the same film thickness, but this is not the only option. The film thicknesses of EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the film thicknesses of EL layers 113R, 113G, and 113B to thicknesses corresponding to the optical path length that intensifies the light emitted by each. This enables the realization of a microcavity structure and improves the color purity of the light emitted from each light-emitting element. 【0585】 The pixel electrode 111R is connected to the conductive layer 112a2 of transistor 206R via openings provided in the insulating layers 110_2, 106_2, 195, and 235 located on the conductive layer 112a2. Furthermore, since the conductive layer 112a2 of transistor 206R and the conductive layer 112b1A of transistor 205R are connected via the conductive layer 115, the pixel electrode 111R is also connected to the conductive layer 112b1A of transistor 205R. 【0586】 Similarly, the pixel electrode 111G is connected to the conductive layer 112a2 of transistor 206G and the conductive layer 112b1A of transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112a2 of transistor 206B and the conductive layer 112b1A of transistor 205B. 【0587】The ends of the pixel electrodes 111R, 111G, and 111B are covered by an insulating layer 237. The insulating layer 237 functions as a partition (also called a bank or spacer). The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the insulating layer 237 can be made of a material that can be used for the insulating layer 235. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. In addition, the insulating layer 237 electrically insulates adjacent light-emitting elements from each other. 【0588】 The common electrode 135 is a continuous film provided in common to the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The common electrode 135, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed by the same process as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. 【0589】 In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light. 【0590】 Furthermore, a conductive film that transmits visible light can also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can be reflected by the reflective layer and extracted from the display device. 【0591】As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include indium tin oxide (ITO), In-Si-Sn oxide (ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, such materials include aluminum-containing alloys (aluminum alloys) such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-magnesium alloys and silver-containing alloys such as silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like. 【0592】 It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element. 【0593】The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a visible light transmittance (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable. 【0594】 The EL layers 113R, 113G, and 113B are each provided in an island-like configuration. In Figure 56, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 56, but this is not the only case. In other words, adjacent EL layers can not overlap and can be configured to be separated from each other. Furthermore, in a display device, it is possible to have a configuration in which both adjacent EL layers overlap and adjacent EL layers do not overlap and are separated from each other. 【0595】 Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material. 【0596】 Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials. 【0597】The light-emitting layer may also consist of one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). The one or more types of organic compounds may include one or both of materials with high hole transport properties (hole transport materials) and materials with high electron transport properties (electron transport materials). Furthermore, bipolar materials (materials with high electron and hole transport properties) or TADF materials may be used as the one or more types of organic compounds. 【0598】 The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting element. 【0599】 The EL layer may have, in addition to the light-emitting layer, one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may also have a configuration that includes either or both a bipolar material and a TADF material. 【0600】 The light-emitting element can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating. 【0601】A light-emitting element can be configured as either a single structure (having only one light-emitting unit) or a tandem structure (having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. In a tandem structure, multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be created. Furthermore, compare...

Claims

It comprises a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer. The second transistor comprises a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a fifth insulating layer. The third transistor comprises a third semiconductor layer, a seventh conductive layer, a fifth conductive layer, a sixth conductive layer, and a fifth insulating layer. The first insulating layer is provided on the first conductive layer, The second conductive layer is provided on the first insulating layer, The first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer. Within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. The fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, The third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening. The second insulating layer is provided on the third conductive layer so as to fill the first opening, The fourth conductive layer is provided on the second insulating layer such that it has a region that overlaps with the first transistor. The seventh conductive layer is provided on the second insulating layer in a region different from the fourth conductive layer. The third insulating layer is provided on the fourth conductive layer and the seventh conductive layer, The fifth conductive layer is provided on the third insulating layer, The third insulating layer and the fifth conductive layer have a second opening that reaches the fourth conductive layer and a third opening that reaches the seventh conductive layer, Within the second opening, the second semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the third insulating layer, and the side surface of the fifth conductive layer. Within the third opening, the third semiconductor layer is provided in contact with the upper surface of the seventh conductive layer, the side surface of the third insulating layer, and the side surface of the fifth conductive layer. The fifth insulating layer is provided in contact with the upper surface of the second semiconductor layer and the upper surface of the third semiconductor layer, respectively. The sixth conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has regions that overlap with the second opening and the third opening, respectively. Semiconductor equipment. 　 In claim 1, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each an oxide semiconductor layer containing indium. The first insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The third insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each contain silicon and nitrogen. The seventh insulating layer and the tenth insulating layer each contain silicon and oxygen, The second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Semiconductor equipment. 　 In claim 1 or claim 2, The fourth insulating layer and the second insulating layer have a fourth opening that reaches the second conductive layer. An eighth conductive layer is provided so as to fill the fourth opening, The eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the fourth conductive layer, respectively. Semiconductor equipment. 　 In claim 1 or claim 2, The first insulating layer, the fourth insulating layer, and the second insulating layer each have a fifth opening that reaches the first conductive layer. An eighth conductive layer is provided so as to fill the fifth opening, The eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the fourth conductive layer, respectively. Semiconductor equipment. 　 It comprises a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer. The second transistor comprises a second semiconductor layer, a first conductive layer, a fourth conductive layer, a third conductive layer, and a fourth insulating layer. The third transistor comprises a third semiconductor layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a fifth insulating layer. The first insulating layer is provided on the first conductive layer, The second conductive layer and the fourth conductive layer are each provided in different regions on the first insulating layer. The first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer. The first insulating layer and the fourth conductive layer have a second opening that reaches the first conductive layer. Within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. Within the second opening, the second semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the fourth conductive layer. The fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer and the upper surface of the second semiconductor layer, The third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has regions that overlap with the first opening and the second opening, respectively. The second insulating layer is provided on the third conductive layer so as to fill the first opening and the second opening, respectively. The fifth conductive layer is provided on the second insulating layer such that it has a region that overlaps with the first transistor. The third insulating layer is provided on the fifth conductive layer, The sixth conductive layer is provided on the third insulating layer, The third insulating layer and the sixth conductive layer have a third opening that reaches the fifth conductive layer. Within the third opening, the third semiconductor layer is provided in contact with the upper surface of the fifth conductive layer, the side surface of the third insulating layer, and the side surface of the sixth conductive layer. The fifth insulating layer is provided in contact with the upper surface of the third semiconductor layer, The seventh conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has a region that overlaps with the third opening. Semiconductor equipment. 　 In claim 5, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each an oxide semiconductor layer containing indium. The first insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The third insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each contain silicon and nitrogen. The seventh insulating layer and the tenth insulating layer each contain silicon and oxygen, The second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Semiconductor equipment. 　 In claim 5 or claim 6, The fourth insulating layer and the second insulating layer have a fourth opening that reaches the second conductive layer. An eighth conductive layer is provided so as to fill the fourth opening, The eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the fifth conductive layer, respectively. Semiconductor equipment. 　 In claim 5 or claim 6, The fourth insulating layer, the second insulating layer, and the third insulating layer each have a fifth opening that reaches the second conductive layer. An eighth conductive layer is provided so as to fill the fifth opening, The eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the sixth conductive layer, respectively. Semiconductor equipment. 　 It comprises a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer. The second transistor comprises a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a fifth insulating layer. The third transistor comprises a third semiconductor layer, a fourth conductive layer, a seventh conductive layer, a sixth conductive layer, and a fifth insulating layer. The first insulating layer is provided on the first conductive layer, The second conductive layer is provided on the first insulating layer, The first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer. Within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. The fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, The third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening. The second insulating layer is provided on the third conductive layer so as to fill the first opening, The fourth conductive layer is provided on the second insulating layer such that it has a region that overlaps with the first transistor. The third insulating layer is provided on the fourth conductive layer, The fifth conductive layer and the seventh conductive layer are each provided in different regions on the third insulating layer. The third insulating layer and the fifth conductive layer have a second opening that reaches the fourth conductive layer. The third insulating layer and the seventh conductive layer have a third opening that reaches the fourth conductive layer. Within the second opening, the second semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the third insulating layer, and the side surface of the fifth conductive layer. Within the third opening, the third semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the third insulating layer, and the side surface of the seventh conductive layer. The fifth insulating layer is provided in contact with the upper surface of the second semiconductor layer and the upper surface of the third semiconductor layer, respectively. The sixth conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has regions that overlap with the second opening and the third opening, respectively. Semiconductor equipment. 　 In claim 9, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each an oxide semiconductor layer containing indium. The first insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The third insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each contain silicon and nitrogen. The seventh insulating layer and the tenth insulating layer each contain silicon and oxygen, The second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Semiconductor equipment. 　 In claim 9 or claim 10, The fourth insulating layer, the second insulating layer, and the third insulating layer each have a fourth opening that reaches the second conductive layer. An eighth conductive layer is provided so as to fill the fourth opening, The eighth conductive layer has regions that are in contact with the upper surface of the second conductive layer and the lower surface of the fifth conductive layer, respectively. Semiconductor equipment. 　 In claim 9 or claim 10, The first insulating layer, the fourth insulating layer, the second insulating layer, and the third insulating layer each have a fifth opening that reaches the first conductive layer. An eighth conductive layer is provided so as to fill the fifth opening, The eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the fifth conductive layer, respectively. Semiconductor equipment. 　 It comprises a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer. The second transistor comprises a second semiconductor layer, a fourth conductive layer, the second conductive layer, the third conductive layer, and the fourth insulating layer. The third transistor comprises a third semiconductor layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a fifth insulating layer. The first conductive layer and the fourth conductive layer are each provided in different regions on the same plane. The first insulating layer is provided on the first conductive layer and the fourth conductive layer. The second conductive layer is provided on the first insulating layer, The first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer and a second opening that reaches the fourth conductive layer, Within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. Within the second opening, the second semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. The fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer and the upper surface of the second semiconductor layer, The third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has regions that overlap with the first opening and the second opening, respectively. The second insulating layer is provided on the third conductive layer so as to fill the first opening and the second opening, respectively. The fifth conductive layer is provided on the second insulating layer such that it has a region that overlaps with the first transistor. The third insulating layer is provided on the fifth conductive layer, The sixth conductive layer is provided on the third insulating layer, The third insulating layer and the sixth conductive layer have a third opening that reaches the fifth conductive layer. Within the third opening, the third semiconductor layer is provided in contact with the upper surface of the fifth conductive layer, the side surface of the third insulating layer, and the side surface of the sixth conductive layer. The fifth insulating layer is provided in contact with the upper surface of the third semiconductor layer, The seventh conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has a region that overlaps with the third opening. Semiconductor equipment. 　 In claim 13, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each an oxide semiconductor layer containing indium. The first insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The third insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each contain silicon and nitrogen. The seventh insulating layer and the tenth insulating layer each contain silicon and oxygen, The second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Semiconductor equipment. 　 In claim 13 or claim 14, The first insulating layer, the fourth insulating layer, and the second insulating layer each have a fourth opening that reaches the first conductive layer. An eighth conductive layer is provided so as to fill the fourth opening, The eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the fifth conductive layer, respectively. Semiconductor equipment. 　 In claim 13 or claim 14, The first insulating layer, the fourth insulating layer, the second insulating layer, and the third insulating layer each have a fifth opening that reaches the first conductive layer. An eighth conductive layer is provided so as to fill the fifth opening, The eighth conductive layer has regions that are in contact with the upper surface of the first conductive layer and the lower surface of the sixth conductive layer, respectively. Semiconductor equipment. 　 The first conductive layer, the first insulating film, and the first conductive film are formed in this order. A portion of the first insulating film and the first conductive film is removed to form a first opening that reaches the first conductive layer, and a first insulating layer and a second conductive layer are formed. Within the first opening, a first semiconductor layer is formed in contact with the side surface of the second conductive layer, the side surface of the first insulating layer, and the upper surface of the first conductive layer. A second insulating layer is formed in contact with the upper surface of the first semiconductor layer. A third conductive layer is formed in contact with the upper surface of the second insulating layer, having a region that overlaps with the first opening. A third insulating layer is formed on the third conductive layer so as to fill the first opening. A portion of the third insulating layer is removed to form a second opening that reaches the second conductive layer. A fourth conductive layer is formed in contact with the upper surface of the second conductive layer so as to fill the second opening. A fifth conductive layer is formed on the third insulating layer such that it has a region in contact with the upper surface of the fourth conductive layer, and a sixth conductive layer is formed on the third insulating layer in a region different from the fifth conductive layer. A second insulating film and a second conductive film are formed in this order on the fifth conductive layer and the sixth conductive layer, A portion of the second insulating film and the second conductive film is removed to form a second opening reaching the fifth conductive layer and a third opening reaching the sixth conductive layer, and a fourth insulating layer and a seventh conductive layer are formed. Within the second opening, a second semiconductor layer is formed in contact with the side surface of the seventh conductive layer, the side surface of the fourth insulating layer, and the upper surface of the fifth conductive layer; and within the third opening, a third semiconductor layer is formed in contact with the side surface of the seventh conductive layer, the side surface of the fourth insulating layer, and the upper surface of the sixth conductive layer. A fifth insulating layer is formed in contact with the upper surface of the second semiconductor layer and the upper surface of the third semiconductor layer, respectively. An eighth conductive layer is formed in contact with the upper surface of the fifth insulating layer, having a region that overlaps with the second opening and the third opening, respectively. Method for manufacturing semiconductor devices.

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