Systems and methods for surface code architecture

Abstract

Measurement qubits in surface code are used to measure X and Z parities. If one measurement qubit is not available, other measurement qubits are able to perform the missing parity measurements, subject to the connectivity of the processor. Additional couplers may be added between data qubits and other measurement qubits to allow for the missing parity measurements during a surface code cycle. The additional couplers are tunable and can be activated when needed to perform the parity measurements. A processor may comprise fewer measurements qubits and additional couplers so that data qubits are always coupled with measurement qubits, so that one measurement qubit may be used for multiple parity measurements. The additional couplers are tunable and are activated when needed to perform the parity measurements and deactivated otherwise during the surface code cycle.

Description

SYSTEMS AND METHODS FOR SURFACE CODE ARCHITECTURECROSS-REFERENCE TO RELATED APPLICATION

[0001] This patent application claims priority of U.S. Patent Application No. 63 / 723,718, filed on November 22, 2024, the entire disclosure of which is hereby incorporated by reference herein for all purposes.FIELD

[0002] This disclosure generally relates to computer architectures that implement surface code, and in particular to quantum processor architectures that implement modified surface code.BACKGROUNDa Quantum Processor

[0003] A hybrid computing system can include a digital or classical computer communicatively coupled to an analog computer. In some implementations, the analog computer is a quantum computer.

[0004] The digital computer can include a digital processor that can be used to perform classical digital processing tasks described in the present systems and methods. The digital computer can include at least one system memory which can be used to store various sets of computer- or processor-readable instructions, application programs and / or data.

[0005] The quantum computer can include a quantum processor that includes programmable elements such as qubits, couplers, and other devices. A quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include a number of superconducting qubits and associated local bias devices. A superconducting quantum processor may also include couplers (also known as coupling devices) that selectively provide communicative coupling between qubits. The qubits can be read out via a readout system, and the results communicated to the digital computer. The qubits and the couplers can be controlled by a qubit control system and a coupler control system, respectively. In some implementations, the qubit and the coupler control systems can be used to implement quantum annealing on the analog computer.

[0006] The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art willbecome apparent to those of skill in the art upon a reading of the specification and a study of the drawings.

[0007] The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.BRIEF SUMMARY

[0008] A method to operate a quantum processor is described. The quantum processor comprises: a two-dimensional grid of qubits, and the grid of qubit comprises: a first plurality of qubits; a second plurality of qubits; a third plurality of qubits; a fourth plurality of qubits; a first plurality of couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits or a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits; and a second plurality of couplers, wherein each coupler in the second plurality of couplers directly couples qubits in the first and second plurality of qubits that are directly communicatively coupled to at least one qubit in the fourth plurality of qubits via the first plurality of couplers to a next-nearest neighbor qubit in the third plurality of qubits. The method is executed by a digital processor communicatively coupled to the quantum processor. The method comprises: identifying at least one deactivated qubit in the fourth plurality of qubits; deactivating couplers in the first plurality of couplers that directly couple the least one deactivated qubit in the fourth plurality of qubits to its nearest-neighbor qubits in the first plurality of qubits and the second plurality of qubits; activating couplers in the second plurality of couplers directly communicatively coupled to nearest-neighbor qubits in the first and second plurality of qubits of the at least one deactivated qubit in the fourth plurality of qubits; applying a surface code computation and reading out a respective state of each of the qubits in the third and fourth pluralities of qubits.

[0009] The quantum processor may further comprise: a first plurality of analog coupler control lines, each analog coupler control line in the first plurality of analog coupler control lines selectively communicatively coupled to a respective one of the couplers in the first plurality of couplers to transmit analog signals to each of the couplers in the first plurality of couplers; and a second plurality of analog coupler control lines, each analogcouplers control line in the second plurality of analog coupler control lines selectively communicatively coupled to a respective one of the couplers in the second plurality of couplers to transmit analog signals to each of the couplers in the second plurality of couplers; and the method may further include deactivating couplers in the first plurality of couplers by applying a control signal to the first plurality of couplers via the first plurality of analog coupler control lines; and activating couplers by applying control signals to the second plurality of couplers via the second plurality of analog coupler control lines.

[0010] Applying a surface code method may include: applying a pulse signal to qubits in the third and fourth pluralities of qubits to initialize the qubits in the third and fourth pluralities of qubits to a respective ground state; applying a Hadamard transformation to qubits in the third plurality of qubits; concurrently applying: a first CNOT gate using the qubits in the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a second CNOT gate using qubits in the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control; concurrently applying: a third CNOT gate using the qubits in the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a fourth CNOT gate using qubits in the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control; concurrently applying: a fifth CNOT gate using the qubits in the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a sixth CNOT gate using qubits in the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control; concurrently applying: a seventh CNOT gate using the qubits in the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and an eighth CNOT gate using qubits in the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control; and applying a Hadamard transformation to the qubits in the third plurality of qubits.

[0011] The quantum processor may further comprise a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, third, and fourth plurality of qubits to transmit analog signals to each of the qubits in the first, second, third, and fourth plurality of qubits; and the method may include applying a pulse signal to qubits in the third and fourth pluralities of qubits to initialize the qubits in the third and fourth pluralities of qubits to a respective ground state via respective qubit control lines; applying a Hadamard transformation to qubits in the third plurality of qubits via respective qubit control lines; concurrently applying: a first CNOT gate using a first subset of the qubits in the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a second CNOT gateusing qubits in a second subset of the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; concurrently applying: a third CNOT gate using the qubits in the second subset of the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a fourth CNOT gate using qubits in the first subset of the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; concurrently applying: a fifth CNOT gate using the qubits in the second subset of the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a sixth CNOT gate using qubits in the first subset of the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; concurrently applying: a seventh CNOT gate using the qubits in the first subset of the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and an eighth CNOT gate using qubits in the second subset of the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; and applying a Hadamard transformation to qubits in the third plurality of qubits via respective qubit control lines.

[0012] A quantum processor comprises: a two-dimensional grid, and the two- dimensional grid comprises: a first plurality of qubits; a second plurality of qubits; a third plurality of qubits; and a fourth plurality of qubits; a first plurality of parity enforcing couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits or a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits; and a second plurality of couplers, wherein each coupler in the second plurality of couplers directly couple a respective qubit in the first and second plurality of qubits that is directly communicatively coupled to at least one deactivated qubit in the fourth plurality of qubits via the first plurality of couplers to a respective next- nearest neighbor qubit in the third plurality of qubits, wherein each coupler in the second plurality of couplers is selectively activated in response to couplers in the first plurality of couplers that are directly communicatively coupled to the at least one deactivated qubit being deactivated.

[0013] Each coupler in the second plurality of couplers may directly couple respective qubits in the first and second plurality of qubits that are directly communicatively coupledto at least one qubit in the third plurality of qubits via the first plurality of couplers to a respective next-nearest neighbor qubit in the fourth plurality of qubits.

[0014] The quantum processor may further comprise: a first plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the first plurality of couplers to transmit analog signals to each of the couplers in the first plurality of couplers; and a second plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the second plurality of couplers to transmit analog signals to each of the couplers in the second plurality of couplers.

[0015] The quantum processor may further comprise a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, third, and fourth plurality of qubits to transmit analog signals to each of the qubits in the first, second, third, and fourth plurality of qubits.

[0016] Each qubit in the first and second plurality of qubits may be a respective data qubit and each qubit in the third and fourth plurality of qubits may be a respective stabilizer qubit operable to perform parity measurements on nearest-neighbor and next- nearest neighbor data qubits.

[0017] A method to operate a quantum processor is described. The quantum processor comprises: a two-dimensional grid of qubits, and the two-dimensional grid comprises: a first plurality of qubits; a second plurality of qubits; and a third plurality of qubits; a first plurality of parity enforcing couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits; and a second plurality of parity enforcing couplers, wherein each coupler in the second plurality of couplers directly couples qubits in the first and second plurality of qubits to a next-nearest neighbor qubit in the third plurality of qubits. The method is executed by a digital processor communicatively coupled to the quantum processor and the method comprises: applying a surface code computation; and reading out a respective state of each of the qubits in the third pluralities of qubits.

[0018] Applying a surface code method may include: applying a pulse signal to qubits in the third plurality of qubits to initialize the qubits in the third plurality of qubits to a respective ground state; applying a Hadamard transformation to qubits in the third plurality of qubits; concurrently applying: a first CNOT gate using at least one qubit in the second plurality of qubits as a control and using at least one qubits in the third plurality of qubits as a target, and a second CNOT gate using at least one qubits in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as acontrol; concurrently applying: a third CNOT gate using at least one qubit in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a fourth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control; concurrently applying: a fifth CNOT gate using at least one qubits in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a sixth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control; concurrently applying: a seventh CNOT gate using at least qubits in the second plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and an eighth CNOT gate using at least one qubit in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control; and applying a Hadamard transformation to qubits in the third plurality of qubits.

[0019] The quantum processor may further comprise a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, and third plurality of qubits to transmit analog signals to each of the qubits in the first, second, and third plurality of qubits; and the method may include applying a pulse signal to qubits in the third plurality of qubits to initialize the qubits in the third plurality of qubits to a respective ground state via qubit control lines; applying a Hadamard transformation to qubits in the third plurality of qubits via qubit control lines; concurrently applying: a first CNOT gate using at least one qubit in the second plurality of qubits as a control and using at least one qubits in the third plurality of qubits as a target, and a second CNOT gate using at least one qubits in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control via qubit control lines; concurrently applying: a third CNOT gate using at least one qubit in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a fourth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control via qubit control lines; concurrently applying: a fifth CNOT gate using at least one qubits in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a sixth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control via qubit control lines; concurrently applying: a seventh CNOT gate using at least qubits in the second plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and an eighth CNOT gate using at least one qubit in the first plurality of qubits as a target and at least a different onequbit in the third plurality of qubits as a control via qubit control lines; and applying a Hadamard transformation to qubits in the third plurality of qubits via qubit control lines.

[0020] A quantum processor comprises a two-dimensional grid of qubits, the two- dimensional grid comprises: a first plurality of qubits; a second plurality of qubits; and a third plurality of qubits; a first plurality of parity enforcing couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits; and a second plurality of parity enforcing couplers, wherein each coupler in the second plurality of couplers directly couples a respective qubit in the first plurality of qubits to a next-nearest neighbor qubit in the third plurality of qubits or a respective qubit in the second plurality of qubits to a next-nearest neighbor qubit in the third plurality of qubits.

[0021] The quantum processor may further comprise: a first plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the first plurality of couplers to transmit analog signals to each of the couplers in the first plurality of couplers; and a second plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the second plurality of couplers to transmit analog signals to each of the couplers in the second plurality of couplers. The quantum processor may further comprise a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, and third plurality of qubits to transmit analog signals to each of the qubits in the first, second, and third plurality of qubits. Each qubit in the first and second plurality of qubits is a respective data qubit and each qubit in the third plurality of qubits may be a respective stabilizer qubit and each qubit in the third plurality of qubits may be operable to perform parity measurements on nearest-neighbor and next-nearest neighbor data qubits.BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0022] In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not necessarily intended to convey any information regarding the actual shape of theparticular elements, and may have been solely selected for ease of recognition in the drawings.

[0023] Figure 1 is a schematic diagram of a hybrid computing system including a digital computer coupled to a quantum computer, in accordance with the present systems, devices, and methods.

[0024] Figure 2 is a schematic diagram of a portion of a quantum processor implementing a surface code architecture, in accordance with the present systems, devices, and methods.

[0025] Figure 3A is a schematic diagram of a portion of a quantum processor implementing a surface code architecture with additional couplers, in accordance with the present systems, devices, and methods.

[0026] Figure 3B is a schematic diagram of portion of the quantum processor of Figure 3A illustrating analog coupler control lines, in accordance with the present systems, devices, and methods.

[0027] Figure 3C is a schematic diagram of a portion of an alternative quantum processor implementing a surface code architecture with additional couplers, in accordance with the present systems, devices, and methods.

[0028] Figure 4 is a flow diagram of an example surface code method that is performed on a quantum processor with additional couplers, in accordance with the present systems, devices, and methods.

[0029] Figure 5 is a flow diagram illustrating an example surface code implementation method that can be performed in a quantum processor and used in the method of Figure 4, in accordance with the present systems, devices, and methods.

[0030] Figure 6A is a schematic diagram of a portion of a quantum processor implementing a surface code architecture with fewer qubits and additional couplers, in accordance with the present systems, devices, and methods.

[0031] Figure 6B is a schematic diagram of portion of the quantum processor of Figure 6A illustrating analog coupler control lines, in accordance with the present systems, devices, and methods.

[0032] Figure 7 flow diagram of an example surface code method that is performed on the quantum processor with fewer qubits and additional couplers of Figure 6A, in accordance with the present systems, devices, and methods.DETAILED DESCRIPTION

[0033] In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed implementations. However, oneskilled in the relevant art will recognize that implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, quantum computer systems, quantum processors, digital computer systems, digital processors, interfaces, and / or communications networks have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the implementations.

[0034] Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprising” is synonymous with “including,” and is inclusive or open-ended ( / .e., does not exclude additional, unrecited elements or method acts).

[0035] Reference throughout this specification to “one implementation” or “an implementation” means that a particular feature, structure or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrases “in one implementation” or “in an implementation” in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0036] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and / or” unless the context clearly dictates otherwise.

[0037] Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0038] The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0039] Figure 1 illustrates a computing system 100 comprising a digital computer 102. The example digital computer 102 includes one or more digital processors 106 that may be used to perform classical digital processing tasks. Digital computer 102 may further include at least one system memory 122, and at least one system bus 120 that couples various system components, including system memory 122 to digital processor(s) 106. System memory 122 may store one or more sets of processor-executable instructions, which may be referred to as modules 124.

[0040] The digital processor(s) 106 may be any logic processing unit or circuitry (for example, integrated circuits), such as one or more central processing units (“CPUs”),graphics processing units (“GPUs”), digital signal processors (“DSPs”), applicationspecific integrated circuits (“ASICs”), programmable gate arrays (“FPGAs”), programmable logic controllers (“PLCs”), etc., and / or combinations of the same.

[0041] In some implementations, computing system 100 comprises a quantum computer 104, which may include one or more quantum processors 126. Quantum processor 126 may include at least one superconducting integrated circuit. Digital computer 102 may communicate with quantum computer 104 via, for instance, a controller 118. Certain computations may be performed by quantum computer 104 at the instruction of digital computer 102, as described in greater detail herein.

[0042] Digital computer 102 may include a user input / output subsystem 108. In some implementations, the user input / output subsystem includes one or more user input / output components such as a display 110, mouse 112, and / or keyboard 114.

[0043] System bus 120 may employ any known bus structures or architectures, including a memory bus with a memory controller, a peripheral bus, and a local bus. System memory 122 may include non-volatile memory, such as read-only memory (“ROM”), static random-access memory (“SRAM”), Flash NAND; and volatile memory such as random-access memory (“RAM”).

[0044] Digital computer 102 may also include other non-transitory computer- or processor-readable storage media or non-volatile memory 116. Non-volatile memory 116 may take a variety of forms, including: a hard disk drive for reading from and writing to a hard disk (for example, a magnetic disk), an optical disk drive for reading from and writing to removable optical disks, and / or a solid state drive (SSD) for reading from and writing to solid state media (for example NAND-based Flash memory). Non-volatile memory 116 may communicate with digital processor(s) via system bus 120 and may include appropriate interfaces or controllers 118 coupled to system bus 120. Nonvolatile memory 116 may serve as long-term storage for processor- or computer- readable instructions, data structures, or other data (sometimes called program modules or modules 124) for digital computer 102.

[0045] Although digital computer 102 has been described as employing hard disks, optical disks and / or solid-state storage media, those skilled in the relevant art will appreciate that other types of nontransitory and non-volatile computer-readable media may be employed. Those skilled in the relevant art will appreciate that some computer architectures employ nontransitory volatile memory and nontransitory non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory or a solid-state disk that employs integrated circuits to provide non-volatile memory.

[0046] Various processor- or computer-readable and / or executable instructions, data structures, or other data may be stored in system memory 122. For example, system memory 122 may store instructions for communicating with remote clients and scheduling use of resources including resources on the digital computer 102 and quantum computer 104. Also, for example, system memory 122 may store at least one of processor executable instructions or data that, when executed by at least one processor, causes the at least one processor to execute the various algorithms to execute instructions. In some implementations system memory 122 may store processor- or computer-readable calculation instructions and / or data to perform preprocessing, co-processing, and post-processing to quantum computer 104. System memory 122 may store a set of computer interface instructions to interact with quantum computer 104. For example, the system memory 122 may store processor- or computer- readable instructions, data structures, or other data which, when executed by a processor or computer causes the processor(s) or computer(s) to execute one, more or all of the acts of the methods 400, 500 and 700.

[0047] Quantum computer 104 may include at least one digital or analog quantum processor such as quantum processor 126. Quantum computer 104 may be provided in an isolated environment, for example, in an isolated environment that shields the internal elements of the quantum computer from heat, magnetic field, and other external noise. The isolated environment may include a refrigerator, for instance a dilution refrigerator, operable to cryogenically cool the quantum processor, for example to temperature below approximately 1 K.

[0048] Quantum computer 104 may include programmable elements such as qubits, couplers, and other devices (also referred to herein as controllable devices). Qubits may be read out via readout control system 128. Readout results may be sent to other computer- or processor-readable instructions of digital computer 102. Qubits may be controlled via a qubit control system 130. Qubit control system 130 may include on-chip Digital to Analog Converters (DACs) and analog lines that are operable to apply a bias to a target device. Couplers that couple qubits may be controlled via a coupler control system 132. Coupler control system 132 may include tuning elements such as on-chip DACs and analog lines. Qubit control system 130 and coupler control system 132 may be used to implement a quantum annealing schedule as described herein on quantum computer 104. In other implementations, qubit control system 130 and coupler control system 132 may be used to implement a gate or circuit model quantum computation. Programmable elements may be included in quantum processor 126 in the form of an integrated circuit. Qubits and couplers may be positioned in layers of the integratedcircuit that comprise a first material. Other devices, such as readout control system 128, may be positioned in other layers of the integrated circuit that comprise a second material. In accordance with the present disclosure, a quantum processor, such as quantum processor 126, may be designed to perform quantum annealing and / or adiabatic quantum computation or gate or circuit model quantum computation.Examples of quantum processors are described in U.S. Patent No. 7,533,068 and International Patent Publication No. WO2024172854.The two-dimensional surface code

[0049] Surface code is a particular implementation of error-corrected quantum computation (QC), wherein logical qubits are encoded into portions or patches of a square lattice of physical qubits using a two-dimensional low density parity check scheme. In the present disclosure and the appended claims, the term ‘logical qubit’ is intended to denote a plurality of physical qubits linked together by coupling devices that collectively act as a single qubit for the purposes of calculations. The theoretical foundations of two-dimensional surface code may be found in the literature; see for example: Daniel Gottesman (Gottesman, D., 1997, Stabilizer Codes and Quantum Error Correction, URL https: / / arxiv.org / abs / quant-ph / 9705052), Alexi Kitaev and Sergei Bravyi (Bravyi, S., and A. Kitaev, 2005, Phys. Rev. A 71 , 022316), Emanuel Knill (Knill, E., 2004a, Fault-tolerant postselected quantum computation: Schemes, eprint 0402171), Robert Raussendorf and Jim Harrington (Raussendorf, R., and J. Harrington, 2007, Phys. Rev. Lett. 98, 190504), Austin Fowler et a / . (Fowler, A. G. et al., 2012, Phys. Rev. A 86, 032324) and Daniel Litinski (Litinski, D., 2019, Quantum 3, 128, ISSN 2521-327X).

[0050] The ability of surface code to identify errors lies in the separation of a physical qubit lattice into sub-lattices: a first sub-lattice comprises a plurality of data qubits, which can be further differentiated into two sublattices of data qubits, called data-A and data-B qubits, respectively, and second and third sub-lattices that comprise two group of qubits referred to as stabilizer qubits or measure qubits in the present description and the appended claims. The data qubits are typically read out near the end of the computation, or at least at the end of a subroutine or subprocess within that computation. Stabilizer qubits are used to perform parity measurements on their nearest-neighbor data qubits, where the nearest-neighbor data qubits are qubits that are directly communicatively coupled to one another with a single intervening coupler. Each data qubit in an interior of a patch of surface code is coupled to four stabilizer qubits, two of which measure XXXX parity that are referred to as measure-X (Mx) qubits, and two of which measure ZZZZ parity that are referred to as measure-Z (Mz) qubits. There are two-local parity stabilizerson the edges of a patch of surface code, corresponding to either XX parity or ZZ parity measurements, and alternating data qubits on the edges are subject to only three parity measurements. By measuring all stabilizers in a repeated cycle, the entire set of data qubits is projected into a quantum state that is a simultaneous eigenstate of all of the XXXX, ZZZZ, XX, and ZZ operators. Errors are heralded by changes in the individual stabilizer outcomes between successive cycles. Through the use of stabilizers, one may advantageously side-step the restrictions of the no-cloning theorem that prevent explicitly measuring the data qubits to identify errors. A feature of two-dimensional surface code is that it is not necessary to physically correct any identified errors in vivo or “in silica", rather it is sufficient to only track identified errors in classical software and correct any final read of an erroneous physical qubit after a corresponding logical qubit has been read.

[0051] Figure 2 is a schematic diagram of an example portion of a quantum processor 200 implementing 2D surface code in accordance with the present systems, devices, and methods. Quantum processor 200 may, for example, be all or a portion of quantum processor 126 used in hybrid computing system 100 of Figure 1. Quantum processor 200 shows an example implementation of an arrangement of physical qubits to provide one or more logical qubits. A logical qubit is a collection of one or more physical qubits that collectively act as a single qubit for the purposes of calculations. In the example of a gate model quantum algorithm, a logical qubit acts as a single qubit for the purposes of quantum logic operations. However, as discussed below, multiple physical qubits are used to form a single logical qubit to provide quantum error correction and thereby a more fault tolerant logical qubit.

[0052] Quantum processor 200 comprises four pluralities of qubits arranged in a two- dimensional lattice or grid. In at least one implementation, quantum processor 200 comprises a plurality of fluxonium qubits. Fluxonium qubits are described in more details in International Patent Publication No. WQ2023096670A2. In another implementation, quantum processor 200 comprises a plurality of fluxonium qubits with high kinetic inductance material. Kinetic inductance materials are those that have a high normal-state resistivity and / or a small superconducting energy gap, resulting in a larger kinetic inductance per unit of area. In general, total inductance L of a superconducting material is given by L = LK+ LG, where LGis the geometric inductance and LKis the kinetic inductance. The kinetic inductance fraction of a material is characterized as a =Lk.Lg+Lk A material considered to have high kinetic inductance would typically have a in the range of 0.1 < a < 1. In yet another implementation, quantum processor 200 comprises a plurality of transmon qubits.

[0053] Quantum processor 200 comprises a first plurality of qubits shown in Figure 2 with no shading (qubits 201a, 201b, and 201 n called out, and herein also collectively referenced as 201), a second plurality of qubits shown in Figure 2 with solid black shading (qubits 202a, 202b, and 202m called out, and herein also collectively referenced as 202), a third plurality of qubits shown in Figure 2 with vertical shading (qubits 203a, 203b, and 203k called out, and herein also collectively referenced as 203) and a fourth plurality of qubits shown in Figure 2 with broken diagonal shading (qubits 204a, 204b, and 204I called out, and herein also collectively referenced as 204).

[0054] Each qubit in first plurality of qubits 201 is communicatively coupled to at least one qubit in third plurality of qubits 203 and at least one qubit in fourth plurality of qubits 204, where qubits in first plurality of qubits 201 that are not at an edge of the two- dimensional lattice or grid are communicatively coupled to two qubits in third plurality of qubits 203 and two qubit in fourth plurality of qubits 204. Each qubit in second plurality of qubits 202 is communicatively coupled to at least one qubit in third plurality of qubits 203 and at least one qubit in fourth plurality of qubits 204, where qubits in second plurality of qubits 202 that are not at an edge of the two-dimensional lattice or grid are communicatively coupled to two qubits in third plurality of qubits 203 and two qubits in fourth plurality of qubits 204.

[0055] Each qubit in third plurality of qubits 203 is communicatively coupled to at least one qubit in first plurality of qubits 201 and at least one qubit in second plurality of qubits 202, where qubits in third plurality of qubits 203 that are not at an edge of the two- dimensional lattice or grid are communicatively coupled to two qubits in first plurality of qubits 201 and two qubit in second plurality of qubits 202. Each qubit in fourth plurality of qubits 204 is communicatively coupled to at least one qubit in first plurality of qubits 201 and at least one qubit in second plurality of qubits 202, where qubits in fourth plurality of qubits 204 that are not at an edge of the two-dimensional lattice or grid are communicatively coupled to two qubits in first plurality of qubits 201 and two qubits in second plurality of qubits 202.

[0056] First plurality of qubits 201 (also called data-A qubits in the present specification and the appended claims) and second plurality of qubits 202 (also called data-B qubits in the present specification and the appended claims) are data qubits and are used for quantum computation, while third and fourth plurality of qubits 203 and 204 are stabilizer qubits and are used for error detection.

[0057] Quantum processor 200 also includes a first plurality of couplers (couplers 205a, 205b, and 205s are called out, and herein also collectively referred to as 205, and illustrated as edges in the lattice of Figure 2) that provide direct tunable communicativecoupling between pairs of qubits in the two-dimensional lattice. First plurality of couplers 205 are arranged in quantum processor 200 in a two-dimensional lattice or grid. These couplings may be inductive, capacitive, or a combination thereof.

[0058] Each coupler in first plurality of couplers 205 provides direct tunable communicative coupling between one qubit in first plurality of qubits 201 and one of third plurality of qubits 203, or between one qubit in first plurality of qubits 201 and one qubit in fourth plurality of qubits 204, or between one qubit in second plurality of qubits 202 and one of third plurality of qubits 203, or between one qubit in second plurality of qubits 202 and one qubit in fourth plurality of qubits 204.

[0059] In quantum processor 200, each qubit in third plurality of qubits 203 that is not at an edge of quantum processor 200 is communicatively coupled to four other qubits (i.e. , two qubits in first plurality of qubits 201 and two qubits in second plurality of qubits 202) via four couplers 205. Each qubit in fourth plurality of qubits 204 that is not at an edge of quantum processor 200 is communicatively coupled to four other qubits (i.e., two qubits in first plurality of qubits 201 and two qubits in second plurality of qubits 202) via four couplers 205.

[0060] Although the example portion of quantum processor 200 is shown in Figure 2 as comprising nine qubits in first plurality of qubits 201, nine qubits in second plurality of qubits 202, nine qubits in third plurality of qubits 203 and nine qubits in fourth plurality of qubits 204, and 60 couplers in first plurality of couplers 205, a person skilled in the art would understand that the number of qubits and couplers in Figure 2 is for example purposes only and, in other implementation, quantum processor 200 may comprise a different number of physical qubits and couplers.Quantum Gates

[0061] A Hadamard gate (H-gate) is a one-qubit gate that is the concatenation of a rotation by TT about the X-axis of the Bloch sphere followed by a rotation by TT / 2 about the Y-axis. The truth table for this operation reveals that it maps computational basis states (|0); |1)) onto the symmetric and antisymmetric superposition states (|+); |-)) and vice- versa. This operation is typically used to transform a given qubit state between the computational (Z) basis and the superposition (X) basis.

[0062] A CNOT gate is a two-qubit gate wherein one qubit acts as a control and the other qubit is the target that is conditionally manipulated based on the state of the control qubit. The truth table for this operation reveals that it flips the computational state of the target qubit only if the control qubit is in state |1). This produces a particularly interesting effect when the control is in a superposition state: the target state becomes entangledwith that of the control. A basic operation for spreading entanglement across a network of qubits is to start a control qubit in state |0>, apply an H-gate to the control qubit, and then apply a CNOT gate to one or more target qubits initialized in state |0). This process can then be concatenated to propagate entanglement across networks.

[0063] Application of CNOT gates between stabilizer qubits (also called measure qubits in the present disclosure), i.e. , qubits in third and fourth plurality of qubits 203 and 204, and data qubits, i.e., qubits in first plurality of qubits 201 and second plurality of qubits 202, followed by measurement of the stabilizer qubits, i.e., qubits in third and fourth plurality of qubits 203 and 204, projects the entire set of data qubits into a Bell-like entangled state. The state of a logical qubit (i.e., the collective state of all data qubits in first and second plurality of qubits 201 and 202) then becomes encoded into something akin to a two-dimensional repetition code. In the absence of noise and no manipulation of the data qubits, the state of the logical qubit will be a steady state. When errors occur, there will be changes to some parity measurements. Classical post-processing of those changes allows identification of individual errors and correction of the final outcome of a quantum computation accordingly. Examples of error detection processes are described in detail in Fowler et al. (Fowler et al., 2012, Phys. Rev. A 86, 032324). Shared qubit and control lines may be used to provide analog signals to the qubits and couplers of processor 200. An example of shared qubit and control lines is described in detail in International Patent Application No. WO2024172854.Robust Surface Code Architecture

[0064] It is advantageous for a robust integrated circuit implementation of the two- dimensional surface code to function despite the presence of a small number of defective devices. For example, such defects may correspond to devices in which one or more Josephson junctions are modestly outside of specification, for example due to fabrication errors. Since these devices are still responsive to control signals, they can be excluded from the working graph of a quantum processor in a manner that minimizes the impact on neighboring devices. Herein, the term “working graph” denotes the set of qubits and couplers that are available for computation in a quantum processor. It would be advantageous to design a two-dimensional surface code quantum processing unit (QPU) that can function despite such imperfections.

[0065] There are parametric considerations that define an acceptable range of device parameters, depending on a specific QPU. However, there are also coherence specifications that must be met. The presence of strongly coupled two-level systems (TLS) located at an inopportune frequency can render a parametrically on-target qubitincompatible with multiplexed control schemes (see, for example, a description of a multiplexed control scheme in International Patent Application No. WO2024172854). Therefore, it is beneficial to design a two-dimensional surface code architecture with built-in protection against failed qubits.

[0066] Nagayama et al. (Nagayama et al., 2017, New J. Phys. 19 023050) describes stabilizer structures that makes use of SWAP operations when a data qubit is defective and that redirects parity information to working stabilizer qubits when a stabilizer qubit is defective. However, insertion of SWAP operations into the surface code cycle at arbitrary locations within the QPU necessitates resource-intensive customized local control, leading to increased complexity. Therefore, the Nagayama structure is not desirable when implementing scalable control. Auger et al. (Auger et al., 2017, Phys. Rev. A 96, 042316) propose disabling a single data qubit when that qubit is either defective or associated with a defective CNOT operation, or disabling a ring of working data qubits surrounding a defective stabilizer qubit. The primary disadvantage of this approach is that one must alternate the measurement of partially-disabled Z-stabilizers and X- stabilizers in successive surface code cycles via local-scale customization of the surface code cycle. This approach would necessitate additional hardware, leading again to increased complexity. Therefore, the Auger approach may not be desirable when implementing scalable control. Both aforementioned references assume that the complexity of dealing with defective devices can be offloaded to control software that modifies the surface code cycle on a local scale. However, every new local-scale degree of freedom necessitates an additional layer of hardware to route and apply the requisite control signals. Eventually, the additional complexity in control might not be any more efficient than providing built-in redundancy.

[0067] Tang and Miao (Tang and Miao, 2016, Phys. Rev. A 93, 032322) propose implementing a nonplanar graph from which one can select a subset of working devices to form a fully yielded patch of two-dimensional surface code. The Tang and Miao approach introduces nonplanar connectivity which again increases complexity without providing full redundancy. International Patent Application No WO2024172854 provides a scalable surface code implementation that is robust to defective devices at the cost of full redundancy. However, introducing full redundancy by duplicating the surface code architecture requires doubling the number of qubits and control circuitry and additional gate operations. Another undesirable consequence of duplication is overhead in duplicating the circuit and higher cost of swap operations.

[0068] Measure qubits (i.e. , qubits in third and fourth plurality of qubits 203 and 204, respectively) in the surface code are only used to measure X and Z parities. However,there is no restriction on which of these measure qubits measure which parities, other than connectivity to the data qubit to be measured. Therefore, as long as a measure qubit can entangle with a desired data qubit, it can be used to measure the desired parity. In a surface code architecture, shown, for example, in Figure 2, one measure qubit is coupled to four neighboring data qubits to measure their parities, either in the X or Z basis. Figure 2 shows an example of surface code where each measure qubit is designed to measure the parity of its four nearest neighbors. Therefore, if one of these qubits, e.g., a measure-Z qubit, is defective, there will be a hole in the quantum state and therefore an unwanted, additional degree of freedom. This is shown in Figures 3A, 3B and 3C, in which one of the Z-stabilizer qubits is defective (shown with a broken line circle). This unwanted, additional degree of freedom can be fixed by allowing other measure qubits to perform the missing parity measurements. By adding two additional couplers to another measure qubit, one of the X-parity measure qubits is now coupled to all of the four data qubits for which the Z-parity measurement is missing. Therefore, by performing the right gate operations, examples of which are shown in Figures 5 and 6, an X-parity measurement qubit can also measure Z-parity of if its neighboring data qubits. These additional couplers added to measure qubits need to be tunable so that they can be entangled with data qubits depending on the type of measurement required in the surface code cycle. By introducing these additional couplers, there will be an additional way to perform parity measurements, and another qubit may be employed to perform the parity measurements instead of the defective stabilizer qubit.

[0069] Figure 3A is a schematic diagram of a portion of a quantum processor 300a implementing a two-dimensional surface code architecture with additional couplers, in accordance with the present systems, devices, and methods. Quantum processor 300a may, for example, be all or a portion of quantum processor 126 used in hybrid computing system 100 of Figure 1. Quantum processor 300a comprises four pluralities of qubits arranged in a two-dimensional lattice or grid. In at least one implementation, quantum processor 300a comprises a plurality of fluxonium qubits. In another implementation, quantum processor 300a comprises a plurality of fluxonium qubits with high kinetic inductance material. In yet another implementation, quantum processor 300a comprises a plurality of transmon qubits.

[0070] Quantum processor 300a comprises a first plurality of qubits shown in Figure 3A with no shading (qubits 301a and 301b called out, and herein also collectively referenced as 301), a second plurality of qubits shown in Figure 3A with black shading (qubits 302a and 302b called out, and herein also collectively referenced as 302), a third plurality of qubits shown in Figure 3A with vertical shading (qubits 303a, 303b, and 303ccalled out, and herein also collectively referenced as 303), and a fourth plurality of qubits shown in Figure 3A with diagonal shading (qubits 304a and 304b called out, and herein also collectively referenced as 304). Qubit 304b in fourth plurality of qubits 304 is not available for parity measurements (represented by a broken line circle). A person skilled in the art will understand that qubit 304b may be defective and may not be operable or out of functional specifications even if operable. Alternatively, qubit 304b may be functional and operable and the additional couplers still allow for operation of the quantum processor as described below and in Figures 4 and 5 without the use of qubit 304b.

[0071] Each qubit in first plurality of qubits 301 is communicatively coupled to at least one qubit in third plurality of qubits 303 and at least one qubit in fourth plurality of qubits 304, where qubits in first plurality of qubits 301 that are not at an edge of the two- dimensional lattice or grid are communicatively coupled to two qubits in third plurality of qubits 303 and two qubit in fourth plurality of qubits 304. Each qubit in second plurality of qubits 302 is communicatively coupled to at least one qubit in third plurality of qubits 303 and least one qubit in fourth plurality of qubits 304, where qubits in second plurality of qubits 302 that are not at an edge of the two-dimensional lattice or grid are communicatively coupled to two qubits in third plurality of qubits 303 and two qubit in fourth plurality of qubits 304. Each qubit in third plurality of qubits 303 is communicatively coupled to at least one qubit in first plurality of qubits 301 and at least one qubit in second plurality of qubits 302, where qubits in third plurality of qubits 303 that are not at an edge of the two-dimensional lattice or grid are communicatively coupled to two qubits in first plurality of qubits 301 and to two qubits in second plurality of qubits 302. Each qubit in fourth plurality of qubits 304 is communicatively coupled to at least one qubit in first plurality of qubits 301 and at least one qubit in second plurality of qubits 302, where qubits in fourth plurality of qubits 304 that are not at an edge of the two-dimensional lattice or grid are communicatively coupled to two qubits in first plurality of qubits 301 and to two qubits in second plurality of qubits 302.

[0072] First plurality of qubits 301 (data-A qubits) and second plurality of qubits 302 (data-B qubits) are data qubits and are used for quantum computation, while third and fourth plurality of qubits 303 and 304 are stabilizer qubits, measure-X and measure-Z, respectively, and are used for error detection.

[0073] Quantum processor 300a also includes a first plurality of couplers (couplers 305a, 305b, 305c, and 305d are called out, and herein also collectively referred to as 305) that provide direct tunable communicative coupling between pairs of qubits in the two-dimensional lattice or grid. First plurality of couplers 305 are arranged in quantumprocessor 300a in a two-dimensional lattice or grid. These couplings may be either inductive or capacitive, or a combination thereof. Couplers 305 may be used as parity enforcing couplers to find errors in the data qubit by reading out the measure qubits. A parity enforcing coupler is any coupler that is coupled such that the overall energy state of the system has two levels, one when all of the connected qubits have an even number of qubits in a given state, and one when all of the connected qubits have an odd number of qubits in a given state. Examples of parity enforcing couplers are described in International Patent Publication No. WO2021195368A1, US Patent Publication No. 2025 / 0055457, and US Patent No. 12,224,750.

[0074] Each coupler in first plurality of couplers 305 provides direct tunable communicative coupling between one qubit in third plurality of qubits 303 and one qubit in first plurality of qubits 301 , or between one qubit in third plurality of qubits 303 and one qubit in second plurality of qubits 302, or between one qubit in fourth plurality of qubits 304 and one qubit in first plurality of qubits 301, or between one qubit in fourth plurality of qubits 304 and one qubit in second plurality of qubits 302.

[0075] In quantum processor 300a, each qubit in third plurality of qubits 303 that is not at an edge of quantum processor 300a is communicatively coupled to four other qubits (i.e. , two qubits in first plurality of qubits 301 and two qubits in second plurality of qubits 302) via four couplers 305. Each qubit in fourth plurality of qubits 304 that is not at an edge of quantum processor 300a is communicatively coupled to four other qubits (i.e., two qubits in first plurality of qubits 301 and two qubits in second plurality of qubits 302) via four couplers 305.

[0076] However, qubit 304b in fourth plurality of qubits is not available and may not be used for the Z-parity measurements of data qubits 301a, 301b, 302a and 302b, although couplers 305a, 305b, 305c, and 305d in first plurality of couplers 305 provide direct communicative coupling between qubit 304b and qubits 301a, 301b, 302a, and 302b, respectively. Qubit 304b may be defective, or, alternatively, qubit 304b may be operable but not desired to be used for parity measurements of data qubits 301a, 301b, 302a and 302b.

[0077] Quantum processor 300a comprises a second plurality of couplers (couplers 306a, 306b, 306c and 306d called out, and herein also collectively referred to as 306 and illustrated in thicker lines in Figure 3A). Second plurality of couplers 306 provides direct tunable communicative coupling between qubits in first plurality of qubits 301 that are directly coupled to qubit 304b and at least two qubits in the third plurality of qubits 303 that are physically more distant then qubit 304b or have other qubits in between, and between qubits in second plurality of qubits 302 that are directly coupled to qubit 304band at least two qubits in the third plurality of qubits 303 that are physically more distant then qubit 304b or have other qubits in between. In the specific implementation of Figure 3A, two measure-X qubits (i.e. , qubits 303c and 303b) are directly communicatively coupled to six data qubits, instead of four data qubits. Qubits 303c and 303b, for example, are directly communicatively coupled to three data-A qubits and three data-B qubits. Coupler 306a allows for direct communicative coupling between data qubit 302a and measure-X qubit 303c; coupler 306b allows for direct communicative coupling between data qubit 301a and measure-X qubit 303c; coupler 306c allows for direct communicative coupling between data qubit 302b and measure-X qubit 303b; and coupler 306d allows for direct communicative coupling between data qubit 301b and measure-X qubit 303b. Qubit 303c is, for example, a next-nearest neighbor to qubit 302a since there are qubits 303a and 301b (or qubits 304b and 302b) positioned between qubit 302a and qubit 303c. Therefore, second plurality of couplers 306 increase the connectivity of processor 300a compared to processor 200.

[0078] Couplers 306 may be used as parity enforcing couplers. Qubits that are directly communicatively coupled via second plurality of couplers 306 (e.g., qubits 302a and 303c) are called next-nearest neighbor qubits in the present disclosure and the appended claims.

[0079] A person skilled in the art will understand that the arrangement of second plurality of couplers 306 shown in Figure 3A is for example purposes only and, in an alternative implementation, different measure-X qubits may be directly communicatively coupled to data qubits 301a, 301b, 302a, and 302b. For example, in another alternative implementation, only one additional measure-X qubit may be directly communicatively coupled to data qubits 301a, 301b, 302a, and 302b, thereby resulting in four measure-X qubits directly communicatively coupled to five data qubits, instead of four. A person skilled in the art will also understand that a qubit in third plurality of qubits 303 may not be available for parity measurements; therefore, second plurality of couplers 306 provide direct communicative coupling between a measure-Z qubit in fourth plurality of qubits 304 and data qubits that are directly communicatively coupled to the non-available qubit.

[0080] Figure 3B is a schematic diagram of portion 300b of quantum processor 300a of Figure 3A illustrating analog coupler control lines. Portion 300b comprises a subset of first plurality of qubits 301, second plurality of qubits 302, third plurality of qubits 303 and fourth plurality of qubits 304 (qubits 301a, 301b, 302a, 302b, 303b, 303c, and 304b called out for illustration purposes), first plurality of couplers 305 (couplers 305a, 305b, 305c, and 305d called out) and second plurality of couplers 306 (couplers 306a, 306b, 306c, and 306d called out and illustrated in a thicker line in Figure 3B). A person skilledin the art will understand that the number of qubits and the arrangement of couplers in portion 300b is for example purposes only and a different portion of quantum processor 300a may have a different number of qubits and couplers.

[0081] Portion 300b comprises a first plurality of coupler analog control lines (lines 307a, 307b, 307c, and 307d called out, collectively 307) providing control signal to first plurality of couplers 305. First plurality of coupler analog control lines 307 may comprise a plurality of subsets of analog coupler control lines, each addressing a subset of couplers 305, as described in further details in International Patent Application No WO2024172854, and operable to transmit analog signals to couplers 305.

[0082] Portion 300b also comprises a second plurality of coupler analog control lines (lines 308a, 308b, 308c, and 308d called out, collectively 308) providing control signal to second plurality of couplers 306 and operable to transmit analog signals to couplers 306.

[0083] Portion 300b shows qubit control lines (only lines 309a and 309b shown to reduce clutter) which provide tunable control signals to first, second, third and fourth plurality of qubits 301, 302, 303 and 304. Qubit control lines 309 may comprise a plurality of subset of qubit control lines, each addressing first plurality of qubits 301, second plurality of qubits 302, third plurality of qubits 303, and fourth plurality of qubits 304, respectively, as described in further details in International Patent Application No WO2024172854, and are operable to transmit analog signals to qubits 301, 302, 303 and 304.

[0084] Figure 3C is a schematic diagram of a portion of a quantum processor 300c implementing a two-dimensional surface code architecture with additional couplers, in accordance with the present systems, devices, and methods. Quantum processor 300c may, for example, be all or a portion of quantum processor 126 used in hybrid computing system 100 of Figure 1. Quantum processor 300c comprises four pluralities of qubits 301, 302, 303 and 304 arranged in a two-dimensional lattice or grid and is an alternative implementation of processor 300a of Figure 3A.

[0085] Quantum processor 300c comprises second plurality of couplers 306 (couplers 306a, 306b, 306e and 306f called out, and herein also collectively referred to as 306 and illustrated in a thicker line in Figure 3C). Second plurality of couplers 306 provides direct tunable communicative coupling between qubits in first or second plurality of qubits 301 or 302 that are directly coupled to qubit 304b and three qubits in the third plurality of qubits 303. In the specific implementation of Figure 3C, one measure-X qubit (i.e. , qubit 303c) is directly communicatively coupled to six data qubits, instead of four, while two measure-X qubits (i.e., qubits 303d and 303e) are directly communicatively coupled to three data qubits, instead of two. Coupler 306a allows for direct communicative couplingbetween data qubit 302a and measure-X qubit 303c and coupler 306b allows for direct communicative coupling between data qubit 301a and measure-X qubit 303c; coupler 306e allows for direct communicative coupling between data qubit 301b and measure-X qubit 303d and coupler 306f allows for direct communicative coupling between data qubit 302b and measure-X qubit 303e.

[0086] A person skilled in the art will understand that the arrangement of second plurality of couplers 306 is shown in Figure 3C for example purposes only and, in an alternative implementation, different measure-X qubits may be directly communicatively coupled to data qubits 301a, 301b, 302a, and 302b.

[0087] In the example quantum processor 300c, a qubit in the fourth plurality of qubits 304 (a measure-Z qubit) may be defective or not desired to be used for parity measurements; however, a person skilled in the art will also understand that a qubit in third plurality of qubits 303 (a measure-X qubit) may equally be defective or not desired to be used for parity measurements and couplers 306 may be used to provide direct communicative coupling between data qubits directly communicatively coupled to this measure-X qubit and other measure-Z qubits to provide the parity measurements. When couplers 306 are used to provide direct communicative coupling between next-nearest neighbor qubits, couplers 305 that are directly communicatively coupled to a defective qubits may be deactivated.

[0088] Figure 4 is a flow diagram of an example surface code method 400 that is performed on a quantum processor, for example quantum processor 300a of Figure 3A, or quantum processor 300c of Figure 3C, with additional couplers. Method 400 will be described with reference to Figures 3A and 3B.

[0089] Method 400 may be executed by a classical computer, for example digital computer 102 of Figure 1, in communication with a quantum processor. Method 400 comprises acts 401- 407; however, a person skilled in the art will understand that the number of acts is an example, and in some implementations, certain acts may be omitted, further acts may be added, and / or the order of the acts may be changed.

[0090] Method 400 starts at 401 , for example in response to a call from another routine.

[0091] At 402, digital computer 102 evaluates the measure qubits to determine the location of at least one measure qubit (e.g., qubit 304b in fourth plurality of qubits 304)not available for use(e.g., there may be a desire not to use a particular qubit or the qubit may be defective). In future executions of method 400, the information about location of qubits that are not available may be stored in memory, for example systemmemory 122 or non-volatile memory 116, and provided as input to method 400, such that future executions of method 400 skip acts 402 and 403.

[0092] At 403, digital computer 102 sends control signals to quantum processor 300a to deactivate the four couplers in first plurality of couplers 305 (e.g., couplers 305a, 305b, 305c, and 305d) that directly couple qubit 304b to its neighboring qubits in first and second plurality of data qubits 301 and 302 (e.g., data qubits 301a, 301b, 302a and 302b). Couplers 305a, 305b, 305c, and 305d are deactivated via coupler analog control lines 307a, 307b, 307c and 307d, for example by setting the coupling strength to zero. Couplers 305a, 305b, 305c, and 305d may be permanently deactivated and, in future executions of method 400, act 403 may be skipped. Acts 402 and 403 may be part of a calibration process and the information about qubits that are not available may be stored in memory, for example system memory 122 or non-volatile memory 116 and provided as input to method 400, such that future executions of method 400 skip acts 402 and 403.

[0093] At 404, digital computer 102 sends control signals to quantum processor 300a to activate second plurality of couplers 306 (e.g., couplers 306a, 306b, 306c, and 306d) between qubits in first and second plurality of data qubits 301 and 302 that are directly communicatively coupled to qubit 304b (e.g., data qubits 301a, 301b, 302a and 302b) and at least two qubits in third plurality of qubits 303 (e.g., measure-X qubits 303b and 303c). Second plurality of couplers 306 are activated via coupler analog control lines 308a, 308b, 308c and 308d.

[0094] At 405, digital computer 102 applies a surface code computation or routine to quantum processor 300a. An example surface code computation is described below with reference to method 500 of Figure 5.

[0095] At 406, digital computer 102 causes states of third and fourth plurality of qubits 303 and 304 (e.g., measure-X (Mx) and measure-Z (Mz) qubits) to be read out. Since qubit 304b in fourth plurality of qubits 304 is not available, digital computer 102 causes the state of qubits 303b and 303c to be read out instead of qubit 304b, thus indicating the state of data qubits 301a, 301b, 302a, and 302b that are directly communicatively coupled to qubit 304b.

[0096] In some implementations, Mx and Mz qubits are read out via readout control system 128. In at least one implementation, a frequency multiplexing resonant readout (FMRR) is employed, as explained in US Patent No 10,938,346. By reading out the stabilizer qubits, one may advantageously side-step the restrictions of the no-cloning theorem that prevent explicitly measuring the data qubits to identify errors. Furtherreadout techniques that may be employed are described in US Patent Application No 63 / 448,537.

[0097] At 407, method 400 terminates, until it is, for example, invoked again.

[0098] Figure 5 is a flow diagram illustrating an example surface code method 500 that can be performed in a quantum processor where at least one measure qubit is unavailable, for example quantum processor 300a of Figure 3A or quantum processor 300c of Figure 3C. Method 500 may be executed by a classical computer, for example digital computer 102 of Figure 1, in communication with the quantum processor. Method 500 may be used to implement act 405 of method 400. Method 500 comprises acts 501- 509; however, a person skilled in the art will understand that the number of acts is an example, and in some implementations, certain acts may be omitted, further acts may be added, and / or the order of the acts may be changed.

[0099] Method 500 starts at 501 , for example in response to a call from another routine, for example at act 405 of method 400.

[0100] Acts 502a and 502b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0101] At 502a, digital computer 102 initializes the qubits (Mx) in third plurality of qubits 303 to their ground state. In at least one implementation, digital computer 102 may cause a pulse to be applied to the Mx qubits via qubit control line 309 to cause a rotation about the Z-axis of the Bloch sphere.

[0102] At 502b, digital computer 102 initializes the qubits (Mz) in fourth plurality of qubits 304 to their ground state. In at least one implementation, digital computer 102 may cause a pulse to be applied to the Mz qubits via qubit control line 309 to cause a rotation about the Z-axis of the Bloch sphere. Since qubit 304b is not available for use, the deactivated qubit 304b is not initialized to the ground state.

[0103] At 503, digital computer 102 causes a Hadamard gate (H-gate) to be applied to the Mx qubits. In at least one implementation, digital computer 102 causes a pulse to be applied to the Mx qubits via qubit control line 309 to cause a rotation about an axis in the XY-plane. Since at 502a the Mx qubits have been initialized to the energy Eigenbasis ground state |0>, the Mx qubits will then be in the superposition state |+).

[0104] Acts 504a and 504b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0105] At 504a, digital computer 102 causes a first CNOT gate to be applied to at least one qubit in second plurality of qubits 302 (data-B qubits) as a control qubit and to at least one qubit in fourth plurality of qubits 304 (Mz qubits) as a target qubit, except for qubit 304b. One Mx qubit from third plurality of qubits 303 may act as a Mz qubit viasecond plurality of couplers 306, instead of qubit 304b. In one example implementation, digital computer 102 causes first CNOT gate to be applied to qubits 302a and 303c.

[0106] At 504b, digital computer 102 causes a second CNOT gate to be applied to at least one qubit in first plurality of qubits 301 (data-A qubits) as a target qubit and to at least one qubit in third plurality of qubits 303 (Mx qubits) as a control qubit. In one example implementation, digital computer 102 causes second CNOT gate to be applied to qubits 301b and 303a.

[0107] Acts 505a and 505b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0108] At 505a, digital computer 102 causes a third CNOT gate to be applied to at least one qubit in first plurality of qubits 301 (data-A qubits) as a control qubit and to at least one qubit in fourth plurality of qubits 304 (Mz qubits) as a target qubit, except for qubit 304b. One Mx qubit from third plurality of qubits 303 may act as a Mz qubit via second plurality of couplers 306, instead of qubit 304b. In one example implementation, digital computer 102 causes third CNOT gate to be applied to qubits 301b and 303b.

[0109] At 505b, digital computer 102 causes a fourth CNOT gate to be applied to at least one qubit in second plurality of qubits 302 (data-A qubits) as a target qubit and to at least one qubit in third plurality of qubits 303 (Mx qubits) as a control qubit. In one example implementation, digital computer 102 causes fourth CNOT gate to be applied to qubits 302a and 303a.

[0110] Acts 506a and 506b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0111] At 506a, digital computer 102 causes a fifth CNOT gate to be applied to at least one qubit in first plurality of qubits 301 (data-A qubits) as a control qubit and to at least one qubit in fourth plurality of qubits 304 (Mz qubits) as a target qubit, except for qubit 304b. One Mx qubit from third plurality of qubits 303 may act as a Mz qubit via second plurality of couplers 306, instead of qubit 304b. In one example implementation, digital computer 102 causes fifth CNOT gate to be applied to qubits 301b and 304c.

[0112] At 506b, digital computer 102 causes a sixth CNOT gate to be applied to at least one qubit in second plurality of qubits 302 (data-B qubits) as a target qubit and to at least one qubit in third plurality of qubits 303 (Mx qubits) as a control qubit. In one example implementation, digital computer 102 causes sixth CNOT gate to be applied to qubits 302a and 303b.

[0113] Acts 507a and 507b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0114] At 507a, digital computer 102 causes a seventh CNOT gate to be applied to at least one qubit in second plurality of qubits 302 (data-B qubits) as a control qubit and to at least one qubit in fourth plurality of qubits 304 (Mz qubits) as a target qubit, except for qubit 304b. One Mx qubit from third plurality of qubits 303 may act as a Mz qubit via second plurality of couplers 306, instead of qubit 304b. In one example implementation, digital computer 102 causes seventh CNOT gate to be applied to qubits 302a and 304a.

[0115] At 507b, digital computer 102 causes an eighth CNOT gate to be applied to at least one qubit in first plurality of qubits 301 (data-A qubits) as a target qubit and to at least one qubit in third plurality of qubits 303 (Mx qubits) as a control qubit. In one example implementation, digital computer 102 causes eighth CNOT gate to be applied to qubits 301b and 303c.

[0116] At 508, digital computer 102 causes an H-gate to be applied to qubits in third plurality of qubits 303 (Mx qubits). In at least one implementation, digital computer 102 may cause a pulse to be applied to the qubit via qubit control line 309 to cause a rotation about an axis in the XY-plane of the Bloch sphere.

[0117] At 509, method 500 terminates, until it is, for example, invoked again. If method 500 was invoked at act 405 of method 400, control passes to act 406 of method 400.

[0118] As discussed above, and in particular with reference to Figures 3A, 3B, 3C, 4 and 5, additional couplers within the processor architecture that can be selectively enabled to compensate for defective qubits can allow for data qubits to be operated in the presence of defective measure qubits. This principle can also be extended to allow for processor architectures that require fewer measure qubits for each data qubit through the presence of additional couplers.

[0119] The principle of coupling to allow measure qubits to act as both Mx and Mz qubits within a processor fabric can be extended for use as the primary mode of operation in addition to being used to compensate for defective qubits. The presence of additional couplers from data qubits to measure-X qubits, allowing the use of measure-X qubit as measure-Z qubits, can be used to decrease the number of qubits in a quantum processor architecture, thereby decreasing the number of circuit elements associated with qubits. Additionally, using one measure qubit for parity measurement of multiple data qubits reduces the number of corresponding resonators, IO lines, etc., therefore achieving a more compact architecture.

[0120] Figure 6A is a schematic diagram of a portion of an example quantum processor 600a implementing a two-dimensional surface code architecture with fewer qubits and additional couplers relative to quantum processor 300a and 300c of Figures 3A and 3C, respectively, in accordance with the present systems, devices, and methods.

[0121] Quantum processor 600a may, for example, be all or a portion of quantum processor 126 used in hybrid computing system 100 of Figure 1. Quantum processor 600a comprises three pluralities of qubits arranged in a two-dimensional lattice or grid. In at least one implementation, quantum processor 600a comprises a plurality of fluxonium qubits. In another implementation, quantum processor 600a comprises a plurality of fluxonium qubits with high kinetic inductance material. In yet another implementation, quantum processor 600a comprises a plurality of transmon qubits.

[0122] Quantum processor 600a comprises a first plurality of qubits shown in Figure 6A with no shading (qubits 601a, 601b, 601c and 601 d called out, and herein also collectively referenced as 601), a second plurality of qubits shown in Figure 6A with black shading (qubits 602a, 602b, 602c, and 602d called out, and herein also collectively referenced as 602) and a third plurality of qubits shown in Figure 6A with vertical shading (qubits 603a, 603b, 603c, 603d, 603e and 603f called out, and herein also collectively referenced as 603).

[0123] Each qubit in first plurality of qubits 601 is communicatively coupled to at least three qubits in third plurality of qubits 603, where qubits in first plurality of qubits 601 that are not at an edge of the two-dimensional lattice or grid are communicatively coupled to four qubits in third plurality of qubits 603.

[0124] Each qubit in second plurality of qubits 602 is communicatively coupled to at least three qubits in third plurality of qubits 603, where qubits in second plurality of qubits 602 that are not at an edge of the two-dimensional lattice or grid are communicatively coupled to four qubits in third plurality of qubits 603.

[0125] Each qubit in third plurality of qubits 603 is communicatively coupled to at least one qubit in first plurality of qubits 601 and at least one qubit in second plurality of qubits 602, where qubits in third plurality of qubits 603 that are not at an edge of the two- dimensional lattice or grid are communicatively coupled to eight other qubits, four qubits in first plurality of qubits 601 and four qubits in second plurality of qubits 602.

[0126] First plurality of qubits 601 (also called data-A in the present specification and the appended claims) and second plurality of qubits 602 (also called data-B in the present specification and the appended claims) are data qubits and are used for quantum computation, while third plurality of qubits 603 are stabilizer qubits, and are used for error detection, and are able to measure X- and Z-parity of data qubits they are directly communicatively coupled with, as needed.

[0127] Quantum processor 600a also includes a first plurality of couplers (couplers 604a, 604b and 604c are called out, and herein also collectively referred to as 604) that provide direct tunable communicative coupling between pairs of qubits in the two-dimensional lattice or grid. First plurality of couplers 604 are arranged in quantum processor 600a in a two-dimensional lattice or grid. These couplings may be either inductive or capacitive, or a combination thereof. Couplers 604 may be used as parity enforcing couplers to find errors in the data qubit by reading out the state of the data qubits. A parity enforcing coupler is any coupler that is coupled such that the overall energy state of the system has two levels, one when all of the connected qubits have an even number of qubits in a given state, and one when all of the connected qubits have an odd number of qubits in a given state.

[0128] Each coupler in first plurality of couplers 604 provides communicative coupling between one qubit in first plurality of qubits 601 and one of third plurality of qubits 603, or between one qubit in second plurality of qubits 602 and one of third plurality of qubits 603.

[0129] In quantum processor 600a, each qubit in first plurality of qubits 601 that is not at an edge of quantum processor 600a is communicatively coupled to two other qubits (i.e. , two qubits from third plurality of qubits 603) via two couplers 604. Each qubit in second plurality of qubits 602 that is not at an edge of quantum processor 600a is communicatively coupled to two other qubits (i.e., two qubits from third plurality of qubits 603) via two couplers 604.

[0130] Quantum processor 600a comprises a second plurality of couplers (couplers 605a, 605b, 605c and 605d called out, and herein also collectively referred to as 605 and illustrated in a thicker line in Figure 6A). Second plurality of couplers 605 provides direct tunable communicative coupling between a respective qubit in first plurality of qubits 601 and two qubits in the third plurality of qubits 603 or coupling between a respective qubit in second plurality of qubits 602 and two qubits in the third plurality of qubits 603.

[0131] In the specific implementation of Figure 6A, measure qubit 603a in third plurality of qubits 603 is directly communicatively coupled to eight data qubits, instead of four as in quantum processor 300a of Figure 3A, two qubits in first plurality of qubits 601 and two qubits in second plurality of qubits 602 via second plurality of couplers 605, in addition to two qubits in first plurality of qubits 601 and two qubits in second plurality of qubits 602 via first plurality of couplers 604. Qubit 601a of first plurality of qubits 601 is directly communicatively coupled to four qubits in third plurality of qubits 603, instead of two as in quantum processor 300a of Figure 3A; and qubit 602a of second plurality of qubits 602 is directly communicatively coupled to four qubits in third plurality of qubits 603, instead of two as in quantum processor 300a of Figure 3A.

[0132] Couplers in second plurality of couplers 605 allows for direct communicative coupling between data qubits 601 and 602 and additional measure-X qubits 603. Couplers 605 may be used as parity enforcing couplers.

[0133] A person skilled in the art will understand that the arrangement of second plurality of couplers 605 is shown in Figure 6A for example purposes only and, in an alternative implementation, different ones of third plurality of qubits 603 may be directly communicatively coupled to first plurality of qubits 601 and second plurality of qubits 602.

[0134] Figure 6B is a schematic diagram of portion 600b of quantum processor 600a of Figure 6A illustrating analog coupler control lines. Portion 600b comprises a subset of first plurality of qubits 601 , second plurality of qubits 602, and third plurality of qubits 603 (qubits 603b and 603d called out for illustration purposes), first plurality of couplers 604 (couplers 604a, 604b and 604c called out) and second plurality of couplers 605 (couplers 605a, 605b, 605c and 605d called out and illustrated in a thicker line in Figure 6B). A person skilled in the art will understand that the number of qubits and the arrangement of couplers in portion 600b is for example purposes only and a different portion of quantum processor 600a may have a different number of qubit and couplers.

[0135] Portion 600b comprises a first plurality of couplers analog control lines (lines 606a, 606b, 606c and 606d called out, collectively 606) providing control signal to first plurality of couplers 604. First plurality of coupler analog control lines 606 may comprise a plurality of subsets of analog coupler control lines, each addressing a subset of couplers 604, as described in further details in International Patent Application No WO2024172854.

[0136] Portion 600b also comprises a second plurality of coupler analog control lines (lines 607a, 607b, 607c and 607d called out, collectively 607) providing control signal to second plurality of couplers 605.

[0137] Portion 600b shows qubit control lines (lines 608a and 608b called out, collectively 608) providing tunable control signals to first, second and third plurality of qubits 601 , 602 and 603. Qubit control lines 608a, 608b may comprise a plurality of subset of qubit control lines, each addressing first plurality of qubits 601 , second plurality of qubits 602 and third plurality of qubits 603, respectively. Qubit control lines 608 can selectively apply control signals to subsets of qubits, advantageously limiting the number of control lines travelling from room temperature to a quantum processor chip, while maintaining individual control over qubits, as described in further details in International Patent Application No WQ2024172854.

[0138] Figure 7 is a flow diagram of an example surface code method 700 that is performed on a quantum processor, for example quantum processor 600a of Figure 6A,with fewer qubits and additional couplers than quantum processor 300a and 300c of Figures 3A and 3C, respectively. Method 700 will be described with reference to quantum processor 600a of Figure 6A. Method 700 is an example of surface code computation that can be performed on a quantum processor with fewer qubits and additional couplers relative to quantum processor 300a and 300c of Figures 3A and 3C.

[0139] Method 700 may be executed by a classical computer, for example digital computer 102 of Figure 1, in communication with a quantum processor. Method 700 comprises acts 701 , 702, 703, 704a, 704b, 705a, 705b, 706a, 706b, 707a, 707b, 708, 709 and 710; however, a person skilled in the art will understand that the number of acts is an example, and in some implementations, certain acts may be omitted, further acts may be added, and / or the order of the acts may be changed.

[0140] Method 700 starts at 701 , for example in response to a call from another routine.

[0141] At 702, digital computer 102 initializes qubits in third plurality of qubits 603 to their ground state. In at least one implementation, digital computer 102 may cause a pulse to be applied to qubits 603 via qubit control line 608 to cause a rotation about the Z-axis of the Bloch sphere.

[0142] At 703, digital computer 102 causes a Hadamard gate (H-gate) to be applied to qubits 603. In at least one implementation, digital computer 102 causes a pulse to be applied to qubits 603 via qubit control line 608 to cause a rotation about an axis in the XY-plane. Since at 702 qubits 603 have been initialized to the energy Eigenbasis ground state |0>, qubits 603 will then be in the superposition state |+).

[0143] Acts 704a and 704b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0144] At 704a, digital computer 102 causes a first CNOT gate to be applied to qubits in second plurality of qubits 602 (data-B qubits) as control qubits and to third plurality of qubits 603 as target qubits. Qubits 603 are used at 704a as measure-Z qubits. In one example implementation, digital computer 102 causes first CNOT gate to be applied to qubits 602a and 603b.

[0145] At 704b, digital computer 102 causes a second CNOT gate to be applied to qubits in first plurality of qubits 601 (data-A qubits) as target qubits and to qubits in third plurality of qubits 603 as control qubits. Qubits 603 are used at 704a as measure-X qubits. In one example implementation, digital computer 102 causes second CNOT gate to be applied to qubits 601a and 603e.

[0146] Acts 705a and 705b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0147] At 705a, digital computer 102 causes a third CNOT gate to be applied to qubits in first plurality of qubits 601 (data-A qubits) as control qubits and to qubits in third plurality of qubits 603 as target qubits. Qubits 603 are used at 705a as measure-Z qubits. In one example implementation, digital computer 102 causes third CNOT gate to be applied to qubits 601a and 603f.

[0148] At 705b, digital computer 102 causes a fourth CNOT gate to be applied to qubits in second plurality of qubits 602 (data-A qubits) as target qubits and to qubits in third plurality of qubits 603 as control qubits. Qubits 603 are used at 705a as measure-X qubits. In one example implementation, digital computer 102 causes fourth CNOT gate to be applied to qubits 602a and 603c.

[0149] Acts 706a and 706b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0150] At 706a, digital computer 102 causes a fifth CNOT gate to be applied to qubits in first plurality of qubits 601 (data-A qubits) as control qubits and to qubits in third plurality of qubits 603 as target qubits. Qubits 603 are used at 706a as measure-Z qubits. In one example implementation, digital computer 102 causes fifth CNOT gate to be applied to qubits 601a and 603c.

[0151] At 706b, digital computer 102 causes a sixth CNOT gate to be applied to qubits in second plurality of qubits 602 (data-B) as target qubits and to qubits in third plurality of qubits 603 as control qubits. Qubits 603 are used at 706a as measure-X qubits. In one example implementation, digital computer 102 causes sixth CNOT gate to be applied to qubits 602a and 603a.

[0152] Acts 707a and 707b are executed by digital computer 102 in parallel, concurrently, or simultaneously.

[0153] At 707a, digital computer 102 causes a seventh CNOT gate to be applied to qubits in second plurality of qubits 602 (data-B) as control qubits and to qubits in third plurality of qubits 603 as target qubits. Qubits 603 are used at 707a as measure-Z qubits. In one example implementation, digital computer 102 causes seventh CNOT gate to be applied to qubits 602a and 603d.

[0154] At 707b, digital computer 102 causes an eighth CNOT gate to be applied to qubits in first plurality of qubits 601 (data-A) as target qubits and to qubits in third plurality of qubits 603 as control qubits. Qubits 603 are used at 707a as measure-X qubits. In one example implementation, digital computer 102 causes eighth CNOT gate to be applied to qubits 601a and 603a.

[0155] At 708, digital computer 102 causes an H-gate to be applied to qubits in third plurality of qubits 603. In at least one implementation, digital computer 102 may cause apulse to be applied to the qubit via qubit control line 608 to cause a rotation about an axis in the XY-plane of the Bloch sphere.

[0156] At 709, digital computer 102 causes states of third plurality of qubits 603 to be read out. In some implementations, qubits 603 are read out via readout control system 128. In at least one implementation, a frequency multiplexing resonant readout (FMRR) is employed, as explained in US Patent No 10,938,346. By reading out the stabilizer qubits, one may advantageously side-step the restrictions of the no-cloning theorem that prevent explicitly measuring the data qubits to identify errors. Further readout techniques that may be employed are described in US Patent Application No 63 / 448,537.

[0157] At 710, method 700 terminates, until it is, for example, invoked again.

[0158] The above described method(s), process(es), or technique(s) could be implemented by a series of processor readable instructions stored on one or more nontransitory processor-readable media. Some examples of the above described method(s), process(es), or technique(s) method are performed in part by a specialized device such as an adiabatic quantum computer or a quantum annealer or a system to program or otherwise control operation of an adiabatic quantum computer or a quantum annealer, for instance a computer that includes at least one digital processor. The above described method(s), process(es), or technique(s) may include various acts, though those of skill in the art will appreciate that in alternative examples certain acts may be omitted and / or additional acts may be added. Those of skill in the art will appreciate that the illustrated order of the acts is shown for exemplary purposes only and may change in alternative examples. Some of the exemplary acts or operations of the above described method(s), process(es), or technique(s) are performed iteratively. Some acts of the above described method(s), process(es), or technique(s) can be performed during each iteration, after a plurality of iterations, or at the end of all the iterations.

[0159] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Although specific implementations of and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the relevant art. The teachings provided herein of the various implementations can be applied to other methods of quantum computation, not necessarily the exemplary methods for quantum computation generally described above.

[0160] The various implementations described above can be combined to provide further implementations. All of the commonly assigned US patent application publications, US patent applications, foreign patents, and foreign patent applicationsreferred to in this specification and / or listed in the Application Data Sheet are incorporated herein by reference, in their entirety, including but not limited to: US Patent No 10,938,346, International Patent Publication No. W02023096670A2, International Patent Publication No. WO2021195368A1, US Patent Publication No. 2025 / 0055457, US Patent No. 12,224,750 and International Patent Application WO2024172854.

[0161] These and other changes can be made to the implementations in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and the claims, but should be construed to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

CLAIMS1. A method to operate a quantum processor, the quantum processor comprising: a two-dimensional grid of qubits, the grid of qubit comprising: a first plurality of qubits; a second plurality of qubits; a third plurality of qubits; a fourth plurality of qubits; a first plurality of couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest- neighbor qubit in the third plurality of qubits or a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits; and a second plurality of couplers, wherein each coupler in the second plurality of couplers directly couples qubits in the first and second plurality of qubits that are directly communicatively coupled to at least one qubit in the fourth plurality of qubits via the first plurality of couplers to a next-nearest neighbor qubit in the third plurality of qubits; the method executed by a digital processor communicatively coupled to the quantum processor, the method comprising: identifying at least one deactivated qubit in the fourth plurality of qubits; deactivating couplers in the first plurality of couplers that directly couple the least one deactivated qubit in the fourth plurality of qubits to its nearest-neighbor qubits in the first plurality of qubits and the second plurality of qubits; activating couplers in the second plurality of couplers directly communicatively coupled to nearest-neighbor qubits in the first and second plurality of qubits of the at least one deactivated qubit in the fourth plurality of qubits; applying a surface code computation and reading out a respective state of each of the qubits in the third and fourth pluralities of qubits.

2. The method of claim 1 , wherein the quantum processor further comprises: a first plurality of analog coupler control lines, each analog coupler control line in the first plurality of analog coupler control lines selectively communicatively coupled to arespective one of the couplers in the first plurality of couplers to transmit analog signals to each of the couplers in the first plurality of couplers; and a second plurality of analog coupler control lines, each analog couplers control line in the second plurality of analog coupler control lines selectively communicatively coupled to a respective one of the couplers in the second plurality of couplers to transmit analog signals to each of the couplers in the second plurality of couplers; and wherein deactivating couplers in the first plurality of couplers that directly couple the least one deactivated qubit in the fourth plurality of qubits to its nearest-neighbor qubits in the first plurality of qubits and the second plurality of qubits includes deactivating couplers in the first plurality of couplers by applying a control signal to the first plurality of couplers via the first plurality of analog coupler control lines; and activating couplers in the second plurality of couplers includes activating couplers by applying control signals to the second plurality of couplers via the second plurality of analog coupler control lines.

3. The method of claim 1 , wherein applying a surface code method includes: applying a pulse signal to qubits in the third and fourth pluralities of qubits to initialize the qubits in the third and fourth pluralities of qubits to a respective ground state; applying a Hadamard transformation to qubits in the third plurality of qubits; concurrently applying: a first CNOT gate using the qubits in the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a second CNOT gate using qubits in the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control; concurrently applying: a third CNOT gate using the qubits in the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a fourth CNOT gate using qubits in the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control; concurrently applying: a fifth CNOT gate using the qubits in the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a sixth CNOT gate using qubits in the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control; concurrently applying: a seventh CNOT gate using the qubits in the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and an eighth CNOT gate using qubits in the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control; and applying a Hadamard transformation to the qubits in the third plurality of qubits.

4. The method of claim 3, wherein the quantum processor further comprises a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, third, and fourth plurality of qubits to transmit analog signals to each of the qubits in the first, second, third, and fourth plurality of qubits; and wherein: applying a pulse signal to qubits in the third and fourth pluralities of qubits to initialize the qubits in the third and fourth pluralities of qubits to a respective ground state includes applying a pulse signal to qubits in the third and fourth pluralities of qubits to initialize the qubits in the third and fourth pluralities of qubits to a respective ground state via respective qubit control lines; applying a Hadamard transformation to qubits in the third plurality of qubits includes applying a Hadamard transformation to qubits in the third plurality of qubits via respective qubit control lines; concurrently applying: a first CNOT gate using a first subset of the qubits in the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a second CNOT gate using qubits in a second subset of the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control includes concurrently applying: a first CNOT gate using a first subset of the qubits in the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a second CNOT gate using qubits in a second subset of the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; concurrently applying: a third CNOT gate using the qubits in the second subset of the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a fourth CNOT gate using qubits in the first subset of the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control includes concurrently applying: a third CNOT gate using the qubits in the second subset of the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a fourth CNOT gate using qubits in the first subset of the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; concurrently applying: a fifth CNOT gate using the qubits in the second subset of the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a sixth CNOT gate using qubits in the first subset of the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control includesconcurrently applying: a fifth CNOT gate using the qubits in the second subset of the first plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and a sixth CNOT gate using qubits in the first subset of the second plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; concurrently applying: a seventh CNOT gate using the qubits in the first subset of the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and an eighth CNOT gate using qubits in the second subset of the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control includes concurrently applying: a seventh CNOT gate using the qubits in the first subset of the second plurality of qubits as a control and using qubits in the fourth plurality of qubits as a target, and an eighth CNOT gate using qubits in the second subset of the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control via respective qubit control lines; and applying a Hadamard transformation to qubits in the third plurality of qubits includes applying a Hadamard transformation to qubits in the third plurality of qubits via respective qubit control lines.

5. A quantum processor comprising: a two-dimensional grid, the two-dimensional grid comprising: a first plurality of qubits; a second plurality of qubits; a third plurality of qubits; and a fourth plurality of qubits; a first plurality of parity enforcing couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits or a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest- neighbor qubit in the third plurality of qubits or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the fourth plurality of qubits; and a second plurality of couplers, wherein each coupler in the second plurality of couplers directly couple a respective qubit in the first and second plurality of qubits that is directly communicatively coupled to at least one deactivated qubit in the fourth plurality of qubits via the first plurality of couplers to a respective next-nearest neighbor qubit in the third plurality of qubits,wherein each coupler in the second plurality of couplers is selectively activated in response to couplers in the first plurality of couplers that are directly communicatively coupled to the at least one deactivated qubit being deactivated.

6. The quantum processor of claim 5, wherein each coupler in the second plurality of couplers directly couples respective qubits in the first and second plurality of qubits that are directly communicatively coupled to at least one qubit in the third plurality of qubits via the first plurality of couplers to a respective next-nearest neighbor qubit in the fourth plurality of qubits.

7. The quantum processor of any one of the claims 5 and 6, further comprising: a first plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the first plurality of couplers to transmit analog signals to each of the couplers in the first plurality of couplers; and a second plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the second plurality of couplers to transmit analog signals to each of the couplers in the second plurality of couplers.

8. The quantum processor of claim 5, further comprising a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, third, and fourth plurality of qubits to transmit analog signals to each of the qubits in the first, second, third, and fourth plurality of qubits.

9. The quantum processor of claim 5, wherein each qubit in the first and second plurality of qubits is a respective data qubit and each qubit in the third and fourth plurality of qubits is a respective stabilizer qubit operable to perform parity measurements on nearest-neighbor and next-nearest neighbor data qubits.

10. The quantum processor of claim 5, wherein the quantum processor is communicatively coupled to a digital processor, and the digital processor is operable to execute the method of any one of claims 1 through 4.

11. A method to operate a quantum processor, the quantum processor comprising: a two-dimensional grid of qubits, the two-dimensional grid comprising:a first plurality of qubits; a second plurality of qubits; and a third plurality of qubits; a first plurality of parity enforcing couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits; and a second plurality of parity enforcing couplers, wherein each coupler in the second plurality of couplers directly couples qubits in the first and second plurality of qubits to a next-nearest neighbor qubit in the third plurality of qubits; the method executed by a digital processor communicatively coupled to the quantum processor, the method comprising: applying a surface code computation; and reading out a respective state of each of the qubits in the third pluralities of qubits.

12. The method of claim 11 , wherein applying a surface code method includes: applying a pulse signal to qubits in the third plurality of qubits to initialize the qubits in the third plurality of qubits to a respective ground state; applying a Hadamard transformation to qubits in the third plurality of qubits; concurrently applying: a first CNOT gate using at least one qubit in the second plurality of qubits as a control and using at least one qubits in the third plurality of qubits as a target, and a second CNOT gate using at least one qubits in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control; concurrently applying: a third CNOT gate using at least one qubit in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a fourth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control; concurrently applying: a fifth CNOT gate using at least one qubits in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a sixth CNOT gate using at least one qubit in the second plurality ofqubits as a target and at least a different one qubit in the third plurality of qubits as a control; concurrently applying: a seventh CNOT gate using at least qubits in the second plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and an eighth CNOT gate using at least one qubit in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control; and applying a Hadamard transformation to qubits in the third plurality of qubits.

13. The method of claim 12, wherein the quantum processor further comprises a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, and third plurality of qubits to transmit analog signals to each of the qubits in the first, second, and third plurality of qubits; and wherein: applying a pulse signal to qubits in the third plurality of qubits to initialize the qubits in the third plurality of qubits to a respective ground state includes applying a pulse signal to qubits in the third plurality of qubits to initialize the qubits in the third plurality of qubits to a respective ground state via qubit control lines; applying a Hadamard transformation to qubits in the third plurality of qubits includes applying a Hadamard transformation to qubits in the third plurality of qubits via qubit control lines; concurrently applying: a first CNOT gate using at least one qubit in the second plurality of qubits as a control and using at least one qubits in the third plurality of qubits as a target, and a second CNOT gate using at least one qubits in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control includes concurrently applying: a first CNOT gate using at least one qubit in the second plurality of qubits as a control and using at least one qubits in the third plurality of qubits as a target, and a second CNOT gate using at least one qubits in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control via qubit control lines; concurrently applying: a third CNOT gate using at least one qubit in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a fourth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control includes concurrently applying: a third CNOT gate using at least one qubit in the first plurality of qubits as a control and using at least one qubit in the third plurality ofqubits as a target, and a fourth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control via qubit control lines; concurrently applying: a fifth CNOT gate using at least one qubits in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a sixth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control includes concurrently applying: a fifth CNOT gate using at least one qubits in the first plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and a sixth CNOT gate using at least one qubit in the second plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control via qubit control lines; concurrently applying: a seventh CNOT gate using at least qubits in the second plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and an eighth CNOT gate using at least one qubit in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control includes concurrently applying: a seventh CNOT gate using at least qubits in the second plurality of qubits as a control and using at least one qubit in the third plurality of qubits as a target, and an eighth CNOT gate using at least one qubit in the first plurality of qubits as a target and at least a different one qubit in the third plurality of qubits as a control via qubit control lines; and applying a Hadamard transformation to qubits in the third plurality of qubits includes applying a Hadamard transformation to qubits in the third plurality of qubits via qubit control lines.

14. A quantum processor comprising: a two-dimensional grid of qubits, the two-dimensional grid comprising: a first plurality of qubits; a second plurality of qubits; and a third plurality of qubits; a first plurality of parity enforcing couplers, wherein each coupler in the first plurality of couplers directly couples a respective qubit in the first plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits, or a respective qubit in the second plurality of qubits to a respective nearest-neighbor qubit in the third plurality of qubits; anda second plurality of parity enforcing couplers, wherein each coupler in the second plurality of couplers directly couples a respective qubit in the first plurality of qubits to a next-nearest neighbor qubit in the third plurality of qubits or a respective qubit in the second plurality of qubits to a next-nearest neighbor qubit in the third plurality of qubits.

15. The quantum processor of claim 14, further comprising: a first plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the first plurality of couplers to transmit analog signals to each of the couplers in the first plurality of couplers; and a second plurality of analog coupler control lines selectively communicatively coupled to each of the couplers in the second plurality of couplers to transmit analog signals to each of the couplers in the second plurality of couplers.

16. The quantum processor of claim 14, further comprising a plurality of qubit control lines, each qubit control line selectively communicatively coupled to a respective one of the qubits in the first, second, and third plurality of qubits to transmit analog signals to each of the qubits in the first, second, and third plurality of qubits.

17. The quantum processor of claim 14, wherein each qubit in the first and second plurality of qubits is a respective data qubit and each qubit in the third plurality of qubits is a respective stabilizer qubit and each qubit in the third plurality of qubits is operable to perform parity measurements on nearest-neighbor and next-nearest neighbor data qubits.

18. The quantum processor of claim 14, wherein the quantum processor is communicatively coupled to a digital processor, and the digital processor is operable to execute the method of any one of claims 11 through 13.

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