Rail-based power management interface and protocol
The PMIC with grouped VRCs and shared reference circuits addresses inconsistent power delivery in SOCs, ensuring reliable power distribution and preventing malfunctions by balancing load currents and synchronizing voltage changes.
WO2026128390A1PCT designated stage Publication Date: 2026-06-18POWERLATTICE TECHNOLOGIES INC
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- POWERLATTICE TECHNOLOGIES INC
- Filing Date
- 2025-12-08
- Publication Date
- 2026-06-18
AI Technical Summary
⚠Technical Problem
The challenge of inconsistent and unstable power delivery on power rails in System on Chip (SOC) due to mismatched regulation circuitry and load demands, leading to performance variations and malfunctions.
⚗Method used
A configurable power management integrated circuit (PMIC) with an array of micro-integrated voltage regulator cells (VRCs) that are grouped and driven by a shared reference circuit, using location-based parameter settings and rail identifiers to ensure consistent and reliable power delivery across power rails.
🎯Benefits of technology
Ensures consistent and reliable power delivery, preventing malfunctions and enhancing the performance and stability of the SOC by balancing load currents and synchronizing voltage changes across power rails.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure US2025058634_18062026_PF_FP_ABST
Abstract
This application is directed to power management in an electronic system that includes a plurality of power rails configured to provide a plurality of rail voltages, a plurality of power chiplets coupled to the power rails, and a power broadcast interface coupled to the power chiplets. Each power chiplet includes a plurality of voltage regulator cells (VRCs), and each respective VRC is configured to output a respective programmable rail voltage to a respective power rail. The power broadcast interface broadcasts a power control command to the plurality of power chiplets, and the power control command includes at least a rail identifier identifying a first power rail. Each of a subset of power chiplets decodes the power control command, and selects a respective set of VRCs among the plurality of respective VRCs based on the rail identifier to provide power to the first power rail.
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