Interconnect system, method, device, medium, and program product

Abstract

The present application discloses an interconnect system, a method, a device, a medium, and a program product in the technical field of computers. In the present application, N signal enhancement modules comprised in each host can enhance communication signals, thereby ensuring the quality of the communication signals transmitted to the interior of the host and the quality of signals transmitted outward from the host. Moreover, each switching module in each host can reserve a host address space for communication with other hosts; and if a host to which any switching module belongs establishes a communication connection with other hosts, the switching module records, in the host address space reserved for other hosts, an access path from the host to other hosts, such that access from the local host to other hosts can be achieved according to the access path, thereby achieving fast communication between different hosts while ensuring the quality of the communication signals.

Description

An interconnection system, method, apparatus, medium, and program product

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411996694.9, filed with the Chinese Patent Office on December 31, 2024, entitled “An Interconnection System, Method, Apparatus, Medium and Program Product”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to an interconnection system, method, apparatus, medium and program product. Background Technology

[0004] Currently, in multi-host interconnection schemes, the multi-host interconnection path based on network interface cards is relatively complex, with high data transmission latency and overhead, low port forwarding efficiency between hosts, and is not suitable for processing high real-time tasks.

[0005] Therefore, how to improve the data forwarding efficiency between hosts is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide an interconnection system, method, apparatus, medium, and program product to improve the data forwarding efficiency between hosts. The specific solution is as follows:

[0007] In a first aspect, this application provides an interconnection system, comprising: multiple hosts and N switching devices for interconnecting different hosts;

[0008] Each host includes: multiple GPUs interconnected, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to N switching devices;

[0009] Among them, the N switching modules are used to: reserve host address space for communication with other hosts; if the host establishes a communication connection with other hosts, record the access path from the host to other hosts in the host address space, and access other hosts according to the access path.

[0010] In some embodiments, within each host, different GPUs are interconnected in pairs via downstream interfaces; any GPU is connected to a processor via an upstream interface; and any GPU is connected to a signal enhancement module via a switching module.

[0011] In some embodiments, the N switching modules are used to: enumerate multiple GPUs in the host and allocate corresponding module address fields to each of the multiple GPUs in the host.

[0012] In some embodiments, at least one processor is configured to: enumerate multiple GPUs in the host and assign corresponding host address domains to each of the multiple GPUs in the host.

[0013] In some embodiments, the N switching modules are used to: map the module address domains of the same GPU in the host to the host address domains, and record the mapping relationship.

[0014] In some embodiments, the N switching modules are used to: receive access data containing a host address field; perform address translation on the access data according to the module address field mapped by the host address field; and perform data transmission based on the address-translated access data.

[0015] In some embodiments, the N switching modules are used to: receive access data containing module address fields; perform address translation on the access data according to the host address field mapped by the module address fields; and perform data transmission based on the address-translated access data.

[0016] In some embodiments, the N switching modules are used to: if the host establishes a communication connection with other hosts, record the port forwarding relationship between the current switching module, the switching devices between the host and other hosts, and the switching modules in other hosts in the host address space, and access other hosts according to the port forwarding relationship.

[0017] In some embodiments, the N switching modules are used to: reserve multiple host address spaces for communication with multiple other hosts respectively.

[0018] In some embodiments, the N switching modules are used to: receive update instructions for the host address space and modify the host address space according to the update instructions.

[0019] In some embodiments, the N switching modules are used to: if the host establishes a communication connection with multiple other hosts, record the access paths from the host to the multiple other hosts in multiple host address spaces, and access the multiple other hosts according to the access paths of the multiple other hosts.

[0020] In some embodiments, the N switching modules are used to: reserve GPU address space for communication with any GPU in other hosts; if the host establishes a communication connection with other hosts, then communicate with the corresponding GPU in other hosts according to the access path from the host to other hosts and the GPU address space.

[0021] In some embodiments, the N switching modules are used to: reserve multiple GPU address spaces corresponding to multiple GPUs in other hosts for communication.

[0022] Secondly, this application provides an interconnection method applicable to any host in an interconnection system, comprising:

[0023] Reserve host address space in at least one switching module in the host for communication with other hosts;

[0024] If a host establishes a communication connection with other hosts in the interconnected system, it records the access path from its host to other hosts in the host's address space and accesses other hosts according to the access path.

[0025] Each host in the interconnect system includes: multiple GPUs interconnected with each other, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to the N switching devices in the interconnect system.

[0026] Thirdly, this application provides an interconnection method applied to a switching module, comprising:

[0027] Reserve host address space for communication with other hosts;

[0028] If the host to which the switching module belongs establishes a communication connection with other hosts, the access path from the host to other hosts is recorded in the host address space, and other hosts are accessed according to the access path;

[0029] The switching modules are located in each host in the interconnect system. Each host in the interconnect system includes: multiple GPUs interconnected with each other, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules. The N signal enhancement modules are respectively connected to N switching devices in the interconnect system.

[0030] In some embodiments, it also includes:

[0031] Reserve multiple host address spaces for communication with multiple other hosts separately.

[0032] In some embodiments, it also includes:

[0033] Reserve GPU address space for communication with any GPU in other hosts;

[0034] If the host establishes a communication connection with another host, it will communicate with the corresponding GPU in the other host according to the access path from the host to the other host and the GPU address space.

[0035] Fourthly, this application provides an electronic device, comprising:

[0036] Memory, used to store computer programs;

[0037] A processor for executing computer programs to implement the aforementioned disclosed interconnection method.

[0038] Fifthly, this application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed interconnection method when executed by a processor.

[0039] Sixthly, this application provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed interconnection method.

[0040] As can be seen from the above scheme, this application provides an interconnection system, including: multiple hosts and N switching devices for interconnecting different hosts; wherein, each host includes: multiple GPUs interconnected with each other, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to the N switching devices; wherein, the N switching modules are used to: reserve host address space for communication with other hosts; if the host establishes a communication connection with other hosts, record the access path from the host to other hosts in the host address space, and access other hosts according to the access path.

[0041] As can be seen, the beneficial effects of this application are as follows: the N signal enhancement modules included in each host can enhance the communication signal, ensuring the communication quality sent to the host and the quality of the signals sent out by the host; furthermore, each switching module in the host can reserve host address space for communication with other hosts; if any host to which a switching module belongs establishes a communication connection with other hosts, then the switching module records the access path from its own host to other hosts in the host address space reserved for other hosts, so that access from the local host to other hosts can be realized according to this access path, thereby realizing fast communication between different hosts, and the communication signal is guaranteed, that is, improving the data forwarding efficiency between hosts.

[0042] Correspondingly, the interconnection method, device, medium, and program product provided in this application also have the above-mentioned technical effects. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in some embodiments of this application or in the prior art, the accompanying drawings used in the description of some embodiments or in the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0044] Figure 1 is a schematic diagram of an interconnection system disclosed in this application;

[0045] Figure 2 is a schematic diagram of another interconnection system disclosed in this application;

[0046] Figure 3 is a schematic diagram of the interconnection between the two host nodes disclosed in this application;

[0047] Figure 4 is a schematic diagram of an address mapping disclosed in this application;

[0048] Figure 5 is a flowchart of an interconnection method disclosed in this application;

[0049] Figure 6 is a schematic diagram of an electronic device disclosed in this application;

[0050] Figure 7 is a server structure diagram provided in this application;

[0051] Figure 8 is a terminal structure diagram provided in this application;

[0052] Figure 9 is a schematic diagram of the address mapping implemented by the GPU in the host provided in this application;

[0053] Figure 10 is a schematic diagram of the interconnection between multiple GPU servers provided in this application;

[0054] Figure 11 is a schematic diagram of the GPU interface provided in this application. Detailed Implementation

[0055] The technical solutions of some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on some embodiments of this application, all other instances obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] Currently, Ethernet technology, combined with specific topologies, can interconnect multiple GPUs within a single rack, creating large-scale multi-computing power interconnection cluster systems and effectively improving computing density. While Ethernet technology can build high-bandwidth domains, it suffers from high latency. For example, in deep learning model training, data and parameters need to be frequently exchanged between multiple GPUs. Excessive communication latency can prolong training time and affect training efficiency. Therefore, in multi-host interconnection schemes, network interface card (NIC)-based multi-host interconnection paths are complex, with high data transmission latency and overhead, and low port forwarding efficiency between hosts, making them unsuitable for handling high real-time tasks. To address this, this application provides an interconnection scheme that improves data forwarding efficiency between hosts.

[0057] Referring to Figure 1, some embodiments of this application disclose an interconnection system, including: multiple hosts and N switching devices for interconnecting different hosts. Each host includes: multiple interconnected computing devices, N switching modules connected to the multiple computing devices, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to the N switching devices. The computing devices are GPUs.

[0058] In some embodiments of this application, there is a one-to-one correspondence between the switching modules and signal enhancement modules within the host, thereby ensuring the data transmission quality through the switching modules. Furthermore, the number of switching devices, switching modules, and signal enhancement modules is equal, thus ensuring a relatively balanced communication load on the switching devices. Both the switching modules and switching devices can be implemented based on a PCIe switch. Communication between devices within the host is achieved via PCIe, while communication between different hosts is achieved via CDFP (400 gigabits / second pluggable input / output components). The signal enhancement module can be a plug-in card or an integrated circuit module. PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. Alternatively, one switching module within the host may connect to multiple signal enhancement modules.

[0059] In one example, N switching modules are used to: reserve host address space for communication with other hosts; if the host establishes a communication connection with other hosts, record the access path from the host to other hosts in the host address space, and access other hosts according to the access path. Specifically, if the host establishes a communication connection with other hosts, record the port forwarding relationships between the current switching module, the switching devices between the host and other hosts, and the switching modules in other hosts in the host address space, and access other hosts according to the port forwarding relationships.

[0060] It should be noted that a single switching module can reserve host address space for multiple hosts, enabling its host to communicate with multiple hosts. Therefore, in one implementation, N switching modules are used to: reserve multiple segments of host address space for communication with multiple other hosts. Correspondingly, if the host establishes communication connections with multiple other hosts, the access paths from the host to each of the other hosts are recorded in the multiple host address spaces, and the host accesses the other hosts according to these access paths. Furthermore, the switching modules can also modify the reserved host address space. Therefore, in one implementation, N switching modules are used to: receive host address space update instructions and modify the host address space according to the update instructions.

[0061] In one implementation, within each host, different GPUs are interconnected in pairs via downstream interfaces; any GPU is connected to a processor via an upstream interface; and a signal enhancement module is connected between any GPU and its connected switching module. That is, a signal enhancement module also enhances the communication signal between the GPU and its connected switching module, ensuring the quality of communication sent to the GPU and the quality of signals sent out by the GPU. The downstream interface can be implemented as a southbound interface, allowing different GPUs to interconnect in pairs via southbound interfaces, enabling interconnection of devices from different manufacturers. It can also be based on software-defined networking to implement functions such as link discovery, topology management, policy formulation, and entry distribution. The upstream interface can be implemented as a northbound interface, providing network access and network management interfaces for the GPU.

[0062] It should be noted that within the same host, each GPU is controlled by both the host processor and the switching module it is connected to. Therefore, the same GPU corresponds to both a host address domain allocated by the host processor and a module address domain allocated by the switching module. The mapping and conversion between these two address domains is implemented by the switching module. In one implementation, N switching modules are used to: enumerate multiple GPUs in the host and allocate corresponding module address domains to each GPU in the host. Correspondingly, at least one processor is used to: enumerate multiple GPUs in the host and allocate corresponding host address domains to each GPU in the host. Correspondingly, the N switching modules are used to: map the module address domains and host address domains of the same GPU in the host and record the mapping relationship. Based on this, when data is transmitted within the same host through the switching modules, there are two cases: Case 1: The host sends data to the GPU, then the N switching modules are used to: receive access data containing the host address domain; perform address translation on the access data according to the module address domain mapped from the host address domain; and perform data transmission based on the address-translated access data. Scenario 1: When the GPU sends data to the host, the N switching modules are used for: receiving access data containing the module address field; performing address translation on the access data according to the host address field mapped to the module address field; and transmitting data based on the address-translated access data. It is evident that within the same host, whether the host sends data to the GPU or the GPU sends data to the host, the corresponding switching modules along the transmission path implement the mutual mapping and translation between the GPU's module address field and the host address field.

[0063] In some embodiments of this application, the GPU can be a device with high computing power, such as a GPU or FPGA. Furthermore, each GPU on any host can be accessed by other hosts simultaneously, in addition to being accessed by the local host. In one implementation, N switching modules are used to: reserve GPU address spaces corresponding to communication with any GPU on other hosts; if the host establishes a communication connection with other hosts, then communicate with the corresponding GPUs on other hosts according to the access path from the host to the other hosts and the GPU address spaces. Multiple GPU address spaces are reserved for communication with multiple GPUs on other hosts. See Figure 9 for a detailed diagram of the GPU address mapping. Each host's address space is independent and does not affect others; the address mapping method maps all hosts' GPUs to each host's address space. For example, in Figure 9, while HOST 01 accesses HOST 01GPU00 using address 0x1_0000_0000 (HOST Address), HOST N can access the same GPU using address 0x2_0000_0000.

[0064] As can be seen, in some embodiments of this application, the N signal enhancement modules included in each host can enhance the communication signal, ensuring the communication quality sent to the host and the quality of the signal sent out by the host; and each switching module in the host can reserve host address space for communication with other hosts; if the host to which any switching module belongs establishes a communication connection with other hosts, then the switching module records the access path from its own host to other hosts in the host address space reserved for other hosts, so that access from the local host to other hosts can be realized according to this access path, thereby realizing fast communication between different hosts and ensuring the communication signal, that is, improving the data forwarding efficiency between hosts.

[0065] It's worth noting that PCIe switches provide a more direct data transmission path. Data doesn't need to go through complex network protocol stacks and multiple layers of network devices, reducing latency and overhead. In latency-sensitive applications, this direct communication method can significantly improve system performance while avoiding network congestion and interference. This makes data transmission between GPUs more stable and efficient, better meeting the needs of applications with high real-time requirements.

[0066] Referring to Figure 2, a 64-card system using PCIe switch interconnection includes: 8 host nodes, each equipped with 8 GPUs. The 64 GPU cards are efficiently interconnected via a PCIe Switch BOX consisting of 4 PCIe Switches. Each host node is an AI server, containing 8 GPUs interconnected in pairs. The GPU interconnection between host nodes is as follows: the host node connects to its internal signal enhancement module via a PCIe Switch; then, a CDFP cable connects the internal signal enhancement module to the PCIe Switch BOX. Within the PCIe Switch BOX, forwarding may occur through multiple PCIe Switches. Thus, via a CDFP cable, the PCIe Switch BOX connects to the internal signal enhancement module of another host node, and then cross-host interconnection between GPUs is achieved through a PCIe Switch within the host node. In Figure 2, A00 represents GPU00, meaning A represents a GPU; one host node includes 8 GPUs.

[0067] In some embodiments of this application, different GPUs are interconnected in pairs through downstream interfaces; any GPU is connected to a processor through an upstream interface. For details, please refer to the interconnection diagram between multiple GPU servers shown in Figure 10 and the GPU interface diagram shown in Figure 11.

[0068] In one example, the interconnection between two host nodes can be seen in Figure 3. In Figure 3, multiple compute nodes within a single host node 0 constitute a UBB (Universal Base Board), which is connected to a PCIe switch within the host node via a signal enhancement module. This PCIe switch is connected to a PCIe switch box outside the host node via another signal enhancement module. This PCIe switch box is connected to a signal enhancement module within another host node 1, as detailed in Figure 3. Figure 3 shows that any two host nodes achieve a symmetrical connection topology based on the PCIe switch box.

[0069] It should be noted that the system illustrated in Figure 2 may include: routing design within host nodes and routing design between host nodes.

[0070] The routing design within the host node includes:

[0071] (1) Before each host node starts, the PCIe Switch inside the host node enumerates and allocates resources for the GPU devices, and assigns a number to the PCIe Switch address field for each GPU. The implementation code is as follows:

[0072] Here, "GPU Switch ID" is the serial number of each PCIe Switch chip within the host node, and there are a total of 4 PCIe Switches within a host node. "GPU BUS" is the configuration space BUS number (bus number) enumerated by the PCIe Switch chip for the corresponding GPU. "GPU Address" is the module address field allocated by the PCIe Switch chip for the corresponding GPU.

[0073] (2) When each host node starts up, the host node's BIOS (Basic Input / Output System) performs device enumeration and resource allocation for the GPU inside the host node. The implementation code is as follows:

[0074] Here, "GPU HOST BUS" is the BUS number enumerated by the host node for the corresponding GPU. "GPU HOST Address" is the host address field assigned by the host node for the corresponding GPU.

[0075] (3) The PCIe Switch chip establishes a correspondence between “GPU Address” and “GPU HOST Address”. This correspondence enables the following: when a host node initiates access to a GPU, it uses the GPU HOST Address. Based on the mapping relationship, the address is converted into the GPU Address allocated by the Switch, and the corresponding GPU inside the host node can be accessed.

[0076] Accordingly, the routing design between host nodes includes:

[0077] (1) Before each host node starts, the PCIe Switch inside the host node enumerates GPU devices and allocates resources, and assigns a number to the PCIe Switch address field for each GPU. The implementation code is as follows:

[0078] (2) When each host node starts up, the host node's BIOS performs device enumeration and resource allocation for the GPU inside the host node. The addresses between each host node are independent. The implementation code is as follows:

[0079] Here, "GPU HOST BUS" is the BUS number enumerated by the host node for the corresponding GPU. "GPU HOST Address" is the host address field assigned by the host node for the corresponding GPU.

[0080] Furthermore, each host node reserves a segment of host addresses for the GPUs of other hosts, as shown in the following code:

[0081] Next, the PCIe Switch establishes the address mapping, as shown in the following code:

[0082] This allows a host node to access the GPU of another host by using address B_0000_0000 from the HOST info. Based on the mapping relationship, this address is translated into an address in the Switch info. Then, the Switch ID is looked up according to the specified Fabric port, and the data packet is forwarded to the PCIe Switch with Switch ID 03. Finally, it is routed to the specified GPU according to Address 0x1_0000_0000, thus completing efficient communication between different host nodes. See Figure 4. In Figure 4, any PCIe Switch1 in host 1 has a mapping logic module Placeholder. This module reserves corresponding address space for host 2 based on MMIO (Memory Mapped IO). PCIe Switch1 connects to Switch3, which is included in the PCIe Switch BOX outside the host, via port FP. Switch3 connects to the FP port of PCIe Switch2 in host 2, thus enabling the access path from host 1 to host 2.

[0083] The PCIe Switch Fabric interconnection scheme proposed in some embodiments of this application can be flexibly expanded to achieve efficient interconnection of multiple PCIe Switches and efficient point-to-point communication between downstream ports of different host nodes without relying on upstream port forwarding, which greatly improves communication efficiency.

[0084] It should be noted that any switching device in a PCIe Switch BOX also includes: a CPLD (Complex Programming Logic Device), a management controller, a baseboard controller, a network switching chip, and a UART (Universal Asynchronous Receiver / Transmitter) chip. This enables hardware-level monitoring, management, and fault detection for each host system, collecting and monitoring the host system's operational status in real time. It can also connect to numerous sensors to read environmental conditions and control temperature via fans. Furthermore, it supports other system management functions, including remote power control, serial LAN, server host and memory monitoring, and error logging. When the system controller diagnoses a fault, it provides a comprehensive and intuitive display via panel indicator lights using optical path diagnostics, clearly indicating host system faults and issuing warnings.

[0085] Since the management of individual computing nodes is very important in large-scale cluster systems, some embodiments of this application also implement overall out-of-band management of computing nodes, with main functions including: device monitoring, log management, fault diagnosis, configuration management, etc.

[0086] Hardware monitoring: The host monitors the hardware of the compute nodes via an out-of-band path through the host's management chip (BMC, Baseboard Management Controller) using the I2C bus protocol. This monitoring includes the compute node's status, board temperature, voltage, and other sensor data. It collects compute node status data for fault location and sends control codes to various chips to perform continuity testing, hardware configuration, module reset, and fault isolation. Temperature monitoring: The management chip dynamically acquires the heat dissipation requirements and temperature information needed for the compute node's operating environment, such as compute node temperature, memory temperature, and inlet / outlet air vent temperatures. Voltage monitoring: It accesses the power supply chip to dynamically acquire board-level voltage status.

[0087] Fault Diagnosis and Log Management: The BMC (Block Controller) chip can obtain error information such as overvoltage, undervoltage, and overtemperature from the compute node via the I2C (Inter-Integrated Circuit) bus protocol. It can also obtain the compute node's serial number, firmware version, driver version, chip operating voltage, and board power consumption. When a compute node fails, the BMC records the real-time monitoring logs to the local file system. Field technicians can export the logs through the BMC web page or other tools to analyze, troubleshoot, and resolve the problem.

[0088] Configuration Management: Supports configuration of software such as network, users, and alarms, and supports importing and exporting configuration files.

[0089] In terms of computing node management, the computing unit and management unit are decoupled and standardized, separating common management, security, and control functions from the computing unit. This ensures compatibility with different computing and management platforms, supports unified management of multiple interfaces and multi-core modules, and meets the needs of different application scenarios. The management unit needs to implement computing power allocation and management, multi-core module voltage regulation and power consumption management to ensure high-efficiency system design; monitor resource utilization, I / O (Input / Output) throughput, and resource health status; achieve coordinated power-on / off, centralized management of resources and topology to ensure system availability; and enable on-demand rapid deployment and automatic management of hardware resources, monitoring of key resource information and fault management, intelligent fault location and recovery to ensure computing system reliability. The system management module is responsible for unified management, providing operation and maintenance capabilities through standardized service interfaces, and achieving integrated monitoring, fault early warning, and visualized management.

[0090] The following describes an interconnection method provided by some embodiments of this application. The interconnection method described below can be referred to in conjunction with other embodiments described herein.

[0091] Referring to Figure 5, some embodiments of this application disclose an interconnection method applied to a switching module, including:

[0092] S501. Reserve host address space for communication with other hosts.

[0093] S502. If the host to which the switching module belongs establishes a communication connection with other hosts, the access path from the host to other hosts is recorded in the host address space, and other hosts are accessed according to the access path.

[0094] In some embodiments, the switching modules are located in any host within the interconnect system. The interconnect system includes multiple hosts and N switching devices for interconnecting different hosts. Each host includes multiple interconnected GPUs, N switching modules connected to the GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are each connected to the N switching devices. There is a one-to-one correspondence between the switching modules and the signal enhancement modules within each host, thereby ensuring the quality of data transmission through the switching modules. Furthermore, the number of switching devices, switching modules, and signal enhancement modules is equal, thereby ensuring a relatively balanced communication load on the switching devices. Both the switching modules and switching devices can be implemented based on a PCIe switch. Communication between devices within a host is achieved via PCIe, and communication between different hosts is achieved via CDFP. The signal enhancement modules can be plug-in cards or integrated circuit modules.

[0095] Within the same host, each GPU is controlled by both the host processor and the switching module it is connected to. Therefore, each GPU corresponds to both a host address domain allocated by the host processor and a module address domain allocated by the switching module. The mapping and conversion between these two address domains is implemented by the switching module. Thus, in one implementation, the switching module enumerates multiple GPUs within the host and allocates corresponding module address domains to each GPU. In another implementation, the switching module maps the module address domains of the same GPU within the host to the host address domains and records the mapping relationship; wherein the host address domains are obtained by the host's basic input / output system enumerating multiple GPUs within the host and allocating them to each GPU.

[0096] Accordingly, the switching module receives access data containing the host address field; performs address translation on the access data according to the module address field mapped to the host address field; and performs data transmission based on the address-translated access data. Similarly, the switching module receives access data containing the module address field; performs address translation on the access data according to the host address field mapped to the module address field; and performs data transmission based on the address-translated access data. It is evident that within the same host, whether the host sends data to the GPU or the GPU sends data to the host, the corresponding switching module on the transmission path implements the mutual mapping and translation between the module address field and the host address field of the same GPU.

[0097] In one implementation, the system further includes: reserving multiple host address spaces for communication with multiple other hosts respectively; reserving GPU address spaces for communication with any GPU in other hosts; if the host establishes a communication connection with other hosts, then communication is performed with the corresponding GPU in the other hosts according to the access path from the host to the other hosts and the GPU address spaces. The switching module reserves GPU address spaces for communication with any GPU in other hosts; if the host establishes a communication connection with other hosts, then communication is performed with the corresponding GPU in the other hosts according to the access path from the host to the other hosts and the GPU address spaces. Multiple GPU address spaces are reserved for communication with multiple GPUs in other hosts respectively.

[0098] In one implementation, the switching module records the port forwarding relationships between the current switching module, the switching devices between its host and other hosts, and the switching modules in other hosts within the host address space; and accesses other hosts according to the port forwarding relationships.

[0099] In one implementation, the switching module reserves multiple host address spaces for communication with multiple other hosts. Thus, a single switching module can reserve host address spaces for multiple hosts, enabling its host to communicate with multiple hosts. The switching module can also modify the reserved host address spaces; it receives update instructions for the host address spaces and modifies them accordingly.

[0100] For more specific details regarding the working processes of various modules and units in some embodiments of this application, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0101] As can be seen, some embodiments of this application provide an interconnection method that enables fast communication between different hosts and ensures reliable communication signals, thereby improving the data forwarding efficiency between hosts.

[0102] The following describes another interconnection method provided by some embodiments of this application. The interconnection method described below can be referred to in conjunction with other embodiments described herein.

[0103] Some embodiments of this application disclose an interconnection method applied to any host in an interconnection system, comprising: reserving a host address space in at least one switching module in the host for communication with other hosts; if the host establishes a communication connection with other hosts in the interconnection system, recording the access path from the host to other hosts in the host address space, and accessing other hosts according to the access path; wherein each host in the interconnection system includes: multiple GPUs interconnected to each other, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to N switching devices in the interconnection system.

[0104] The host also uses a switching module to reserve GPU address spaces for communication with any GPU in other hosts. If the host establishes a communication connection with other hosts, it communicates with the corresponding GPUs in those hosts according to the access path from the host to the other hosts and the GPU address spaces. Multiple GPU address spaces are reserved for communication with multiple GPUs in other hosts.

[0105] For more specific details regarding the working processes of various modules and units in some embodiments of this application, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0106] As can be seen, some embodiments of this application provide an interconnection method that enables fast communication between different hosts and ensures reliable communication signals, thereby improving the data forwarding efficiency between hosts.

[0107] The following describes an electronic device provided by some embodiments of this application. The electronic device described below can be referred to in conjunction with other embodiments described herein. The electronic device provided by some embodiments of this application may be a functional module such as a switching module or switching device from the foregoing embodiments.

[0108] Referring to Figure 6, some embodiments of this application disclose an electronic device, including:

[0109] Memory 601 is used to store computer programs;

[0110] Processor 602 is configured to execute computer programs to implement the methods disclosed in some of the embodiments described above.

[0111] In some embodiments of this application, when the processor executes the computer program stored in the memory, it may specifically implement the following steps: reserving a host address space for communication with other hosts; if the host to which the switching module belongs establishes a communication connection with other hosts, then recording the access path from the host to other hosts in the host address space, and accessing other hosts according to the access path.

[0112] In some embodiments of this application, when the processor executes a computer program stored in memory, it may specifically implement the following steps: enumerating multiple GPUs in the host and allocating corresponding module address fields to each of the multiple GPUs in the host.

[0113] In some embodiments of this application, when the processor executes a computer program stored in memory, it may specifically implement the following steps: mapping the module address domain of the same GPU in the host to the host address domain and recording the mapping relationship; wherein, the host address domain is obtained by the host's basic input / output system enumerating multiple GPUs in the host and allocating them to the multiple GPUs in the host respectively.

[0114] In some embodiments of this application, when a processor executes a computer program stored in memory, it may specifically implement the following steps: receiving access data containing a host address field; performing address translation on the access data according to the module address field mapped by the host address field; and performing data transmission based on the address-translated access data.

[0115] In some embodiments of this application, when a processor executes a computer program stored in memory, it may specifically implement the following steps: receiving access data containing a module address field; performing address translation on the access data according to the host address field mapped by the module address field; and performing data transmission based on the address-translated access data.

[0116] In some embodiments of this application, when the processor executes a computer program stored in the memory, it may specifically implement the following steps: recording the current switching module, the switching devices between the host and other hosts, and the port forwarding relationships between switching modules in other hosts in the host address space; and accessing other hosts according to the port forwarding relationships.

[0117] In some embodiments of this application, when the processor executes a computer program stored in the memory, it may specifically implement the following steps: reserving multiple host address spaces for communication with multiple other hosts respectively.

[0118] Furthermore, some embodiments of this application also provide an electronic device. This electronic device can be either a server as shown in FIG. 7 or a terminal as shown in FIG. 8. FIG. 7 and FIG. 8 are structural diagrams of the electronic device according to some embodiments, and the content in the figures should not be considered as any limitation on the scope of this application.

[0119] Figure 7 is a schematic diagram of the structure of a server provided in some embodiments of this application. Specifically, the server may include: N processors, N memories, a power supply, a communication interface, an input / output interface, and a communication bus. The memories are used to store computer programs, which are loaded and executed by the processors to implement the relevant steps in the interconnection disclosed in the foregoing embodiments.

[0120] In some embodiments of this application, the power supply is used to provide operating voltage for various hardware devices on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0121] In addition, the memory, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system, computer programs and data, etc., and the storage method can be temporary storage or permanent storage.

[0122] The operating system manages and controls the various hardware devices and computer programs on the server to enable the processor to perform operations and processes on the data in the memory. It can be Windows Server (Microsoft's server operating system), Netware (Novell's network operating system), Unix, Linux, etc. In addition to computer programs capable of performing the interconnection methods disclosed in some of the aforementioned embodiments, the computer programs may further include computer programs capable of performing other specific tasks. The data may include application update information and application developer information.

[0123] Figure 8 is a schematic diagram of the structure of a terminal provided in some embodiments of this application. The terminal may include, but is not limited to, a smartphone, tablet computer, laptop computer, or desktop computer.

[0124] Typically, the terminal in some embodiments of this application includes a processor and a memory.

[0125] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor can be implemented using at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and coprocessors. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which handles computational operations related to machine learning.

[0126] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments of this application, the memory is used to store at least the following computer programs, wherein, after being loaded and executed by a processor, the computer programs are capable of implementing the relevant steps in the interconnection method executed by the terminal side as disclosed in the foregoing embodiments. In addition, the resources stored in the memory may also include operating systems and data, and the storage method may be temporary or permanent storage. The operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, application update information.

[0127] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0128] Those skilled in the art will understand that the structure shown in Figure 8 does not constitute a limitation on the terminal and may include more or fewer components than shown.

[0129] The following describes a non-volatile storage medium provided by some embodiments of this application. The non-volatile storage medium described below can be referred to in conjunction with other embodiments described herein.

[0130] Some embodiments of this application disclose a non-volatile storage medium for storing computer programs, wherein the computer programs, when executed by a processor, implement the interconnection methods disclosed in the aforementioned embodiments. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored thereon include operating systems, computer programs, and data, and the storage method can be temporary storage or permanent storage.

[0131] In some embodiments of this application, when the processor executes a computer program stored in a non-volatile storage medium, it may specifically implement the following steps: reserving a host address space for communication with other hosts; if the host to which the switching module belongs establishes a communication connection with other hosts, then recording the access path from the host to other hosts in the host address space, and accessing other hosts according to the access path.

[0132] In some embodiments of this application, when a processor executes a computer program stored in a non-volatile storage medium, it may specifically implement the following steps: enumerating multiple GPUs in the host and allocating corresponding module address fields to each of the multiple GPUs in the host.

[0133] In some embodiments of this application, when a processor executes a computer program stored in a non-volatile storage medium, it may specifically implement the following steps: mapping the module address fields of the same GPU in the host to the host address fields and recording the mapping relationship; wherein, the host address fields are obtained by the host's basic input / output system enumerating multiple GPUs in the host and allocating them to the multiple GPUs in the host respectively.

[0134] In some embodiments of this application, when a processor executes a computer program stored in a non-volatile storage medium, it may specifically implement the following steps: receiving access data containing a host address field; performing address translation on the access data according to the module address field mapped by the host address field; and transmitting data based on the address-translated access data.

[0135] In some embodiments of this application, when a processor executes a computer program stored in a non-volatile storage medium, it may specifically implement the following steps: receiving access data containing a module address field; performing address translation on the access data according to the host address field mapped by the module address field; and transmitting data based on the address-translated access data.

[0136] In some embodiments of this application, when a processor executes a computer program stored in a non-volatile storage medium, it may specifically implement the following steps: recording the current switching module, the switching devices between the host and other hosts, and the port forwarding relationships between switching modules in other hosts in the host address space; and accessing other hosts according to the port forwarding relationships.

[0137] In some embodiments of this application, when a processor executes a computer program stored in a non-volatile storage medium, it may specifically implement the following steps: reserving multiple host address spaces for communication with multiple other hosts respectively.

[0138] The following describes a computer program product provided by some embodiments of this application. The computer program product described below can be referred to in conjunction with other embodiments described herein.

[0139] Some embodiments of this application disclose a computer program product including a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed interconnection method.

[0140] In some embodiments of this application, when a computer program / instruction is executed by a processor, the following steps can be specifically implemented: reserving a host address space for communication with other hosts; if the host to which the switching module belongs establishes a communication connection with other hosts, then recording the access path from the host to other hosts in the host address space, and accessing other hosts according to the access path.

[0141] In some embodiments of this application, when a computer program / instruction is executed by a processor, the following steps may be specifically implemented: enumerating multiple GPUs in the host and allocating corresponding module address fields to each of the multiple GPUs in the host.

[0142] In some embodiments of this application, when a computer program / instruction is executed by a processor, the following steps can be specifically implemented: mapping the module address domain of the same GPU in the host to the host address domain and recording the mapping relationship; wherein, the host address domain is obtained by the host's basic input / output system enumerating multiple GPUs in the host and allocating them to the multiple GPUs in the host respectively.

[0143] In some embodiments of this application, when a computer program / instruction is executed by a processor, the following steps can be specifically implemented: receiving access data containing a host address field; performing address translation on the access data according to the module address field mapped by the host address field; and transmitting data based on the address-translated access data.

[0144] In some embodiments of this application, when a computer program / instruction is executed by a processor, the following steps can be specifically implemented: receiving access data containing a module address field; performing address translation on the access data according to the host address field mapped by the module address field; and transmitting data based on the address-translated access data.

[0145] In some embodiments of this application, when a computer program / instruction is executed by a processor, the following steps can be specifically implemented: recording the current switching module, the switching devices between the host and other hosts, and the port forwarding relationships between switching modules in other hosts in the host address space; and accessing other hosts according to the port forwarding relationships.

[0146] In some embodiments of this application, when a computer program / instruction is executed by a processor, the following steps may be specifically implemented: reserving multiple host address spaces for communication with multiple other hosts respectively.

[0147] Some embodiments in this specification are described in a progressive manner, and some embodiments focus on the differences from other embodiments. For the same or similar parts between some embodiments, please refer to each other.

[0148] The steps of the methods or algorithms described in conjunction with some of the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM (Compact Disc Read-Only Memory), or any other form of non-volatile storage medium known in the art.

[0149] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An interconnection system, characterized in that, include: Multiple hosts and N switching devices configured to interconnect different hosts; Each host includes: multiple GPUs interconnected with each other, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to the N switching devices; The N switching modules are configured to: reserve host address space for communication with other hosts; if the host establishes a communication connection with other hosts, record the access path from the host to other hosts in the host address space, and access other hosts according to the access path.

2. The interconnection system according to claim 1, characterized in that, Within each host, different GPUs are interconnected in pairs through downstream interfaces; any GPU is connected to a processor through an upstream interface; and any GPU is connected to a signal enhancement module through a switching module.

3. The interconnection system according to claim 1, characterized in that, The N switching modules are configured to enumerate multiple GPUs in the host and allocate corresponding module address fields to each of the multiple GPUs in the host.

4. The interconnection system according to claim 3, characterized in that, The at least one processor is configured to: enumerate multiple GPUs in the host and assign corresponding host address domains to each of the multiple GPUs in the host.

5. The interconnection system according to claim 4, characterized in that, The N switching modules are configured to map the module address fields of the same GPU in the host to the host address fields and record the mapping relationship.

6. The interconnection system according to claim 5, characterized in that, The N switching modules are configured to: receive access data containing a host address field; perform address translation on the access data according to the module address field mapped by the host address field; and perform data transmission based on the address-translated access data.

7. The interconnection system according to claim 5, characterized in that, The N switching modules are configured to: receive access data containing module address fields; perform address translation on the access data according to the host address field mapped by the module address field; and perform data transmission based on the address-translated access data.

8. The interconnection system according to any one of claims 1 to 7, characterized in that, The N switching modules are configured such that if the host establishes a communication connection with another host, they record the port forwarding relationships between the current switching module, the switching devices between the host and other hosts, and the switching modules in other hosts in the host address space, and access other hosts according to the port forwarding relationships.

9. The interconnection system according to any one of claims 1 to 7, characterized in that, The N switching modules are configured to reserve multiple host address spaces that are configured to communicate with multiple other hosts respectively.

10. The interconnection system according to any one of claims 1 to 7, characterized in that, The N switching modules are configured to: receive update instructions for the host address space and modify the host address space according to the update instructions.

11. The interconnection system according to claim 9, characterized in that, The N switching modules are configured such that if the host establishes communication connections with multiple other hosts, the access paths from the host to the multiple other hosts are recorded in multiple host address spaces, and the multiple other hosts are accessed according to the access paths of the multiple other hosts.

12. The interconnection system according to any one of claims 1 to 7, characterized in that, The N switching modules are configured to: reserve GPU address space corresponding to any GPU configured to communicate with other hosts; if the host establishes a communication connection with other hosts, then communicate with the corresponding GPU in other hosts according to the access path from the host to other hosts and the GPU address space.

13. The interconnection system according to claim 12, characterized in that, The N switching modules are configured to reserve multiple GPU address spaces corresponding to multiple GPUs configured to communicate with other hosts.

14. An interconnection method, characterized in that, Applied to any host in an interconnected system, including: In at least one switching module of the host, a host address space is reserved for communication with other hosts; If the host establishes a communication connection with other hosts in the interconnection system, it records the access path from the host to other hosts in the host address space and accesses other hosts according to the access path. Each host in the interconnect system includes: multiple GPUs interconnected with each other, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to N switching devices in the interconnect system.

15. An interconnection method, characterized in that, Applied to switching modules, including: Reserve the address space of hosts configured to communicate with other hosts; If the host to which the switching module belongs establishes a communication connection with other hosts, the access path from the host to other hosts is recorded in the host address space, and other hosts are accessed according to the access path. The switching modules are disposed in each host in the interconnection system. Each host in the interconnection system includes: multiple GPUs interconnected with each other, N switching modules connected to the multiple GPUs, at least one processor connected to the N switching modules, and N signal enhancement modules connected to the N switching modules; the N signal enhancement modules are respectively connected to N switching devices in the interconnection system.

16. The interconnection method according to claim 15, characterized in that, Also includes: Reserve multiple host address spaces that are configured to communicate with multiple other hosts separately.

17. The interconnection method according to claim 15, characterized in that, Also includes: Reserve the GPU address space that is configured to communicate with any GPU in other hosts; If the host establishes a communication connection with another host, it will communicate with the corresponding GPU in the other host according to the access path from the host to the other host and the GPU address space.

18. An electronic device, characterized in that, include: Memory, configured to store computer programs; A processor is configured to execute the computer program to implement the method as described in any one of claims 14 to 17.

19. A non-volatile storage medium, characterized in that, It is configured to store a computer program, wherein the computer program, when executed by a processor, implements the method as described in any one of claims 14 to 17.

20. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the method as described in any one of claims 14 to 17.

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