A signal processing combination performance checking system based on DSP communication test
By using homomorphic replication and empty slot injection modules to perform shadow operations during the idle period of the DSP core, and combining this with time-frequency domain comparison by the performance judgment module, the problem of achieving zero-latency online verification and fault differentiation in the prior art is solved, thereby improving the reliability and maintainability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SHIJICHEN DATA TECH CO LTD
- Filing Date
- 2026-04-14
- Publication Date
- 2026-07-03
AI Technical Summary
Existing technologies struggle to achieve zero-latency online verification of digital signal processors without suspending the mainline, and cannot effectively distinguish between external electromagnetic interference and internal hardware hidden faults, leading to reduced system reliability and maintainability.
The homomorphic replication module captures DSP core parameters in real time, and the empty slot injection module completes shadow calculations during pipeline idle cycles. The performance decision module performs time-domain/frequency-domain weighted comparison and composite decision-making to achieve accurate differentiation of fault types.
It achieves zero-perception, zero-latency online verification of the combined performance of DSP signal processing, improving system reliability and maintainability, and reducing system maintenance costs and downtime.
Smart Images
Figure CN122332233A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of real-time testing technology for digital signal processors, and more specifically to a signal processing combined performance verification system based on DSP communication testing. Background Technology
[0002] In high-speed communication testing systems, the digital signal processor (DSP) core, as the core computing unit, undertakes the critical task of executing complex signal processing algorithms in real time. Its computational accuracy and real-time stability directly determine the overall performance, link reliability, and test coverage of the entire communication testing system. If the DSP core experiences computational deviations or timing anomalies, it will lead to increased bit error rate, signal distortion, protocol parsing failures, and even the collapse of the entire test link.
[0003] In existing technologies, the performance verification of digital signal processors (DSPs) mainly relies on offline testing and actively interrupting the main business process. Offline verification, performed when the system is down or idle, injects standard signals into the DSP using an external dedicated test vector generator, and then uses an external analyzer to collect and compare the output results. While this can accurately verify specific algorithms, it cannot cover the real-time changes in dynamic configuration parameters of the DSP during actual business operations. Furthermore, the test cycle is long and the coverage is low, failing to meet the continuous online monitoring requirements of high-speed communication testing. Actively interrupting the main business process pauses the DSP's main pipeline through software interruption or a hardware watchdog mechanism, switching to verification mode to execute test vector calculations. While this achieves some real-time performance, it introduces a significant business interruption latency, leading to packet loss, synchronization loss, or protocol retransmission in the communication test link, severely impacting test efficiency and system availability.
[0004] Existing technologies struggle to achieve zero-latency online verification without disrupting the mains pipeline, and they also fail to effectively distinguish between external electromagnetic interference and internal hardware occultation. External interference can cause transient bit flips or signal-to-noise ratio degradation, while degradation of computing power within the digital signal processor manifests as context synchronization anomalies or latency jitter. Current verification schemes often employ single-dimensional comparisons, failing to integrate time-domain / frequency-domain features with the second-order derivative of the timing sequence for composite decision-making. Therefore, fault localization is ambiguous, making it difficult to provide clear delimitations of whether external interference causes service degradation or internal hardware occultation within the digital signal processor. This not only increases system maintenance costs and downtime but also reduces overall reliability.
[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this invention is to provide a signal processing combination performance verification system based on DSP communication testing. Through the synergy of three major modules—homomorphic replication, empty slot injection, and performance judgment—it achieves zero-perception, zero-latency online verification of DSP signal processing combination performance, and can accurately distinguish fault types, thereby improving system reliability and maintainability, and solving the problems mentioned in the background art.
[0007] To achieve the above objectives, the present invention provides the following technical solution: a signal processing combined performance verification system based on DSP communication testing, specifically including: a homomorphic replication module, a slot injection module, and a performance decision module;
[0008] Homomorphic copy module: Captures the dynamic configuration parameters of the current DSP core in real time through the hardware sniffing bus and mirrors them to the shadow register;
[0009] Empty slot injection module: Based on the peeping unit, the bubble cycle of the pipeline is identified by the prediction logic. At the moment when the main computing unit is in the waiting cycle, the hardware triggers the operation enable of the shadow register group, inputs the preset feature test vector into the computing engine, and completes a shadow operation.
[0010] Performance Decision Module: The module performs a weighted comparison of the real-time data stream of the main path and the reference data stream of the shadow path in the time and frequency domains using a hardware comparison array, calculates the second derivative of the response delay, and outputs the comprehensive performance factor.
[0011] As a preferred embodiment of the signal processing combined performance verification system based on DSP communication testing described in this invention, wherein:
[0012] The dynamic configuration parameters of the DSP core are captured in real time by a hardware sniffing bus and mirrored to the shadow register.
[0013] Based on the high-sensitivity feature address mapping table preset by the combined verification controller, the parameter register space in the DSP processing core that executes a specific signal processing algorithm is corresponding to the parameter register space.
[0014] The write enable signal and target address of the main DSP core are monitored in real time. When the characteristic address is updated, the data payload of the write operation is captured in parallel without suspending the main stream.
[0015] Based on the hardware triggering mechanism, the data payload is synchronously directed to the corresponding address input terminal of the shadow register group;
[0016] Based on the physical characteristics of dual-port registers, the dynamic configuration parameters are homomorphically stored in the shadow register group according to the strobe signal of the controller within the same clock cycle when the main register group is updated.
[0017] After the mirroring is completed, the characteristic values of the master and mirror registers are checked for consistency through the built-in hardware comparison logic.
[0018] After verification, a lock instruction is issued to put the shadow register group into read-only mode, and a context ready flag is sent to the pipeline's spy unit as a precondition for triggering subsequent verification signal injection.
[0019] As a preferred embodiment of the signal processing combined performance verification system based on DSP communication testing described in this invention, wherein:
[0020] By continuously monitoring the status registers of the main DSP core during the instruction fetch, decode, and execution stages through the spy unit of the instruction pipeline, pipeline pause signals and branch prediction failure flags are extracted to obtain the busy level of the main computing engine in real time.
[0021] Using built-in hardware prediction logic, it predicts at the leading edge of the current instruction cycle whether there will be idle slots in the main computing unit waiting for external storage data or instruction synchronization in the next clock cycle.
[0022] Once a specific vacant slot is identified, the combined verification controller immediately issues a computing power preemption command.
[0023] By using a hardware multiplexer, the input of the computing engine can be temporarily switched to the data output of the shadow register group without severing the main path logical connection.
[0024] At the beginning of the idle period, the shadow register group pushes the feature test vectors preset in the read-only memory to the computing engine in parallel according to the synchronized algorithm context, and completes the shadow operation on the feature test vectors.
[0025] Intermediate and final results generated by the operation are directed to physically independent result buffers;
[0026] One clock cycle before the idle slots expire, the shadow computing process is forcibly terminated and the computing engine access rights are released, achieving zero-latency verification that is perceived by the main business.
[0027] As a preferred embodiment of the signal processing combined performance verification system based on DSP communication testing described in this invention, wherein:
[0028] The combined verification controller extracts real-time business processing results from the main path and extracts the corresponding shadow operation results from the result buffer.
[0029] The two sets of data are aligned at the algorithm logic level through internal clock alignment logic, eliminating time offset;
[0030] The hardware comparison array performs the following metrics in parallel on the aligned data stream: calculates the Euclidean distance between the two sets of vectors to identify bit flips or hard computation errors; performs a fast Fourier transform on the equation output to extract the signal-to-noise ratio loss and out-of-band spurious distribution for evaluating numerical stability.
[0031] The physical cycle from injection into an idle slot to result retrieval for each shadow operation is recorded using a high-precision timer, and the first and second derivatives of the response delay are calculated.
[0032] Based on the preset system state weights, the built-in arithmetic logic unit performs composite operations, the specific formula of which is:
[0033]
[0034] in, This represents the overall performance factor, used to quantify the overall quality of the combined performance of DSP signal processing. Indicates the accuracy weight of the algorithm. This represents the decrease in signal-to-noise ratio (SNR) after the shadow path processes the feature test vectors, compared to the ideal error-free output. This represents the theoretically expected signal-to-noise ratio (SNR) loss after processing the same feature test vector using the same algorithm under ideal hardware conditions and in an interference-free environment. Indicates time deterministic weights, The second derivative represents the response delay;
[0035] The output comprehensive performance factor is compared with a preset threshold array, and a scene determination is made based on the error between the main path and the shadow path.
[0036] If the overall performance factor exceeds the threshold and the main path error is large while the shadow path error is small, it is determined that the service decline is caused by external electromagnetic interference.
[0037] If the overall performance factor exceeds the threshold and both path errors are large, it is determined that the DSP's internal computing power is degraded or the context synchronization is abnormal.
[0038] Based on the delimitation results, an interrupt signal is reported to the main control unit or a hot backup switch is triggered.
[0039] On the other hand, the present invention provides a computer device, including a memory and a processor, wherein the memory stores a computer program, wherein when the computer program is executed by the processor, it implements the steps of a signal processing combination performance verification system based on DSP communication testing as described above.
[0040] On the other hand, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements the steps of a signal processing combination performance verification system based on DSP communication testing as described above.
[0041] The technical effects and advantages provided by the present invention in the above technical solution are as follows:
[0042] (1) The idle slots are predicted in real time by the spy unit of the instruction pipeline, and the hardware multiplexer is used to seize the computing engine instantly when the main computing unit is waiting for external data or instruction synchronization, and the preset feature test vector is injected to complete the shadow operation.
[0043] (2) The entire shadow operation process is strictly limited to the idle slots, and the resources are released seamlessly one clock cycle before the slot ends, so that the main path instruction flow can be seamlessly continued and the main business is completely unaware of the existence of the verification.
[0044] (3) The write enable signal and target address of the main DSP core are captured in real time through the hardware sniffing bus. The data payload is captured in parallel without suspending the main stream. Based on the physical characteristics of the dual-port register, it is homomorphically mirrored to the shadow register group in the same clock cycle.
[0045] (4) Consistency verification is performed through built-in hardware comparison logic. After verification is successful, the shadow register is immediately locked and enters read-only mode to avoid subsequent random updates polluting the verification background. This ensures that the algorithm context used by the shadow operation is completely synchronized with the main business, thus making the shadow result a reliable reference and significantly improving the accuracy and reliability of the verification.
[0046] (5) Through hardware prediction logic, the system anticipates future idle slots at the forefront of the current instruction cycle. Once identified, it issues a preemption command to temporarily switch the input end of the computing engine without severing the main path logic connection. Shadow computation only occupies these previously wasted idle cycles, and the computation results are directed to an independent buffer without requiring additional hardware cores or significantly increasing area overhead. This not only improves the overall computing power utilization but also reduces system power consumption and hardware costs, providing an efficient and feasible solution for online self-verification under a multi-core heterogeneous DSP architecture.
[0047] (6) Perform time-domain / frequency-domain weighted comparison of the real-time data stream of the main path and the reference data stream of the shadow path, and realize normalized fusion judgment through composite formula. Based on the comparison of C value and threshold, as well as the error difference of the main / shadow path, it effectively avoids misjudgment and omission, significantly reduces system maintenance costs and downtime, which is especially critical in high reliability fields such as military communication testing and aerospace telemetry and control. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.
[0049] Figure 1 This is a flowchart of a method for verifying the combined performance of signal processing based on DSP communication testing according to the present invention.
[0050] Figure 2 This is a schematic diagram of a signal processing combined performance verification system based on DSP communication testing according to the present invention. Detailed Implementation
[0051] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.
[0052] Example 1, referring to Figure 1 and Figure 2 This is the first embodiment of the present invention. This embodiment provides a signal processing combination performance verification system based on DSP communication testing, specifically including: a homomorphic replication module, a slot injection module, and a performance decision module;
[0053] Homomorphic copy module: Captures the dynamic configuration parameters of the current DSP core in real time through the hardware sniffing bus and mirrors them to the shadow register;
[0054] The dynamic configuration parameters of the DSP core are captured in real time by a hardware sniffing bus and mirrored to the shadow register.
[0055] Based on the high-sensitivity feature address mapping table preset by the combined verification controller, the parameter register space in the DSP processing core that executes a specific signal processing algorithm is corresponding to the parameter register space.
[0056] The write enable signal and target address of the main DSP core are monitored in real time. When the characteristic address is updated, the data payload of the write operation is captured in parallel without suspending the main stream.
[0057] Based on the hardware triggering mechanism, the data payload is synchronously directed to the corresponding address input terminal of the shadow register group;
[0058] Based on the physical characteristics of dual-port registers, the dynamic configuration parameters are homomorphically stored in the shadow register group according to the strobe signal of the controller within the same clock cycle when the main register group is updated.
[0059] After the mirroring is completed, the characteristic values of the master and mirror registers are checked for consistency through the built-in hardware comparison logic.
[0060] After verification, a lock instruction is issued to put the shadow register group into read-only mode, and a context ready flag is sent to the pipeline's spy unit as a precondition for triggering subsequent verification signal injection.
[0061] Empty slot injection module: Based on the peeping unit, the bubble cycle of the pipeline is identified by the prediction logic. At the moment when the main computing unit is in the waiting cycle, the hardware triggers the operation enable of the shadow register group, inputs the preset feature test vector into the computing engine, and completes a shadow operation.
[0062] By continuously monitoring the status registers of the main DSP core during the instruction fetch, decode, and execution stages through the spy unit of the instruction pipeline, pipeline pause signals and branch prediction failure flags are extracted to obtain the busy level of the main computing engine in real time.
[0063] Using built-in hardware prediction logic, it predicts at the leading edge of the current instruction cycle whether there will be idle slots in the main computing unit waiting for external storage data or instruction synchronization in the next clock cycle.
[0064] Once a specific vacant slot is identified, the combined verification controller immediately issues a computing power preemption command.
[0065] By using a hardware multiplexer, the input of the computing engine can be temporarily switched to the data output of the shadow register group without severing the main path logical connection.
[0066] At the beginning of the idle period, the shadow register group pushes the feature test vectors preset in the read-only memory to the computing engine in parallel according to the synchronized algorithm context, and completes the shadow operation on the feature test vectors.
[0067] Intermediate and final results generated by the operation are directed to physically independent result buffers;
[0068] One clock cycle before the idle slots expire, the shadow computing process is forcibly terminated and the computing engine access rights are released, achieving zero-latency verification that is perceived by the main business.
[0069] Performance Decision Module: The module performs a weighted comparison of the real-time data stream of the main path and the reference data stream of the shadow path in the time and frequency domains using a hardware comparison array, calculates the second derivative of the response delay (i.e., jitter), and outputs a comprehensive performance factor.
[0070] The combined verification controller extracts real-time business processing results from the main path and extracts the corresponding shadow operation results from the result buffer.
[0071] The two sets of data are aligned at the algorithm logic level through internal clock alignment logic, eliminating time offset;
[0072] The hardware comparison array performs the following metrics in parallel on the aligned data stream: calculates the Euclidean distance between the two sets of vectors to identify bit flips or hard computation errors; performs a fast Fourier transform on the equation output to extract the signal-to-noise ratio loss and out-of-band spurious distribution for evaluating numerical stability.
[0073] The physical cycle from injection into an idle slot to result retrieval for each shadow operation is recorded using a high-precision timer, and the first derivative (delay) and second derivative (jitter) of the response delay are calculated.
[0074] Based on the preset system state weights, the built-in arithmetic logic unit performs composite operations, the specific formula of which is:
[0075]
[0076] in, This represents the overall performance factor, used to quantify the overall quality of the combined performance of DSP signal processing. Indicates the accuracy weight of the algorithm. This represents the decrease in signal-to-noise ratio (SNR) after the shadow path processes the feature test vectors, compared to the ideal error-free output. This represents the theoretically expected signal-to-noise ratio (SNR) loss after processing the same feature test vector using the same algorithm under ideal hardware conditions and in an interference-free environment. Indicates time deterministic weights, The second derivative represents the response delay;
[0077] The output comprehensive performance factor is compared with a preset threshold array, and a scene determination is made based on the error between the main path and the shadow path.
[0078] If the overall performance factor exceeds the threshold and the main path error is large while the shadow path error is small, it is determined that the service decline is caused by external electromagnetic interference.
[0079] If the overall performance factor exceeds the threshold and both path errors are large, it is determined that the DSP's internal computing power has degraded or the context synchronization is abnormal (hardware hidden fault).
[0080] Based on the delimitation results, an interrupt signal is reported to the main control unit or a hot backup switch is triggered.
[0081] Example 2
[0082] The following is another embodiment of the present invention, which provides a signal processing combination performance verification system based on DSP communication testing. In order to verify the beneficial effects of the present invention, a simulation experiment is conducted for scientific demonstration.
[0083] A simulation platform was built using a single-core DSP model with a 1GHz clock speed and an 8-stage pipeline as the core to simulate a real communication test environment.
[0084] The main path executes a 16-QAM demodulation algorithm with a length of 1024 points (including FIR filtering, carrier synchronization, equalization, and symbol decision), and the service data stream is a modulated signal with a rate of 100MSPS.
[0085] The shadow path adopts a register mirroring mechanism that is completely homomorphic to the main path, and the feature test vector is a preset linear frequency modulation signal (bandwidth 10 MHz, duration 10 μs).
[0086] The hardware sniffing bus module captures write enable and address signals in real time through the virtual bus interface to achieve homomorphic copying.
[0087] The spy unit uses a branch prediction failure flag and a pause signal to predict the probability of an empty slot of 15%~25% (which is consistent with actual high-load DSP scenarios).
[0088] The performance decision module integrates Euclidean distance, FFT signal-to-noise ratio extraction, and second-order time delay derivative calculation modules. The specific formula for the composite performance factor is as follows:
[0089]
[0090] in, It is 0.7. It is 0.3. The second derivative is the dithering derivative, in units of ns².
[0091] The simulation clock period was set to 1ns, and a total of 10,000 instruction cycles were run, covering three scenarios.
[0092] The three scenarios include:
[0093] Scenario 1 (Baseline Scenario): Uninterrupted pure business operation to verify zero-latency characteristics;
[0094] Scenario 2 (External Interference): Inject Gaussian white noise with a power of -20 dB into the main path data stream to simulate electromagnetic interference and observe the system's ability to identify external interference.
[0095] Scenario 3 (Internal Fault): Inject 5% precision drift (simulating hardware aging) and 1ns metastable jitter into the MAC unit to verify the ability to delineate internal hidden faults.
[0096] Each scenario was simulated 100 times, and the statistical average was taken.
[0097] The simulation results and analysis specifically include:
[0098] (1) Simulation results show that after the introduction of the verification mechanism of this invention, the latency of the main path service instruction flow did not change measurably (the average latency remained at 8.00 ns, and the standard deviation was <0.01 ns), which was completely consistent with the baseline group without verification. The empty slot injection module successfully utilized the predicted idle slots (occupying an average of 18.7 slots per 100 cycles), and the shadow operation occupancy rate fell within the idle period of 100%, with the main path seamless continuity rate reaching 99.98%. The perceived latency of the main service was 0, realizing a truly "zero-perception" online verification.
[0099] (2) When the homomorphic copy module updates each feature address, the mirror delay is strictly controlled within the same clock cycle, and the consistency check pass rate of the master shadow register group is 100%. The Euclidean distance between the shadow operation result and the theoretical golden reference value is 0 (under ideal synchronization conditions), which verifies that the context is completely consistent and avoids the synchronization deviation problem commonly found in traditional shadow technology.
[0100] (3) Under high load conditions with a pipeline utilization rate of 92%, the present invention achieves zero additional overhead for verification computing power through empty slot preemption. Compared with traditional interrupt-type verification (which requires an additional 5%~8% computing power), the computing power utilization rate of this system is increased to 99.2%, and the power consumption is only increased by 0.3% (mainly from the sniffing bus), which fully demonstrates the high-efficiency reuse value of pipeline empty slots.
[0101] (4) The statistical results of the C value output by the performance judgment module are shown in Table 1:
[0102] Scene Main path SNR loss (dB) Shadow path SNR loss (dB) Jittery second derivative (ns²) C value Verdict accuracy Scenario 1 (Normal) 0.12 0.11 0.02 0.18 Normal, no fault 100% Scenario 2 (External Interference) 2.85 0.13 0.45 2.31 External electromagnetic interference 100% Scenario 3 (Internal Failure) 3.21 3.18 1.87 4.12 DSP internal computing power degradation 100%
[0103] Table 1
[0104] The simulation process and results show that in scenario 2, the C value exceeds the preset threshold of 1.5, and the main path error is significantly greater than that of the shadow path, which the system accurately identifies as "external interference." In scenario 3, both paths have large errors and abnormal jitter, which the system accurately identifies as "internal hardware latent fault." The fault location accuracy is 100%, a significant improvement over existing single-dimensional verification methods (accuracy of approximately 65%~75%). Furthermore, the system immediately triggers a hot backup switching signal upon detecting scenario 3, with a switching time of <10ns, ensuring the continuity of communication testing.
[0105] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.
Claims
1. A signal processing combined performance verification system based on DSP communication test, characterized in that, Specifically, it includes: Homomorphic copy module, empty slot injection module, and performance judgment module; Homomorphic copy module: Captures the dynamic configuration parameters of the current DSP core in real time through the hardware sniffing bus and mirrors them to the shadow register; Empty slot injection module: Based on the peeping unit, the bubble cycle of the pipeline is identified by the prediction logic. At the moment when the main computing unit is in the waiting cycle, the hardware triggers the operation enable of the shadow register group, inputs the preset feature test vector into the computing engine, and completes a shadow operation. Performance Decision Module: The module performs a weighted comparison of the real-time data stream of the main path and the reference data stream of the shadow path in the time and frequency domains using a hardware comparison array, calculates the second derivative of the response delay, and outputs the comprehensive performance factor.
2. The signal processing combined performance verification system based on DSP communication testing according to claim 1, characterized in that: In the homomorphic copy module, the dynamic configuration parameters of the DSP core are captured in real time through the hardware sniffing bus and mirrored to the shadow register. Based on the high-sensitivity feature address mapping table preset by the combined verification controller, the parameter register space in the DSP processing core that executes a specific signal processing algorithm is corresponding to the parameter register space. The write enable signal and target address of the main DSP core are monitored in real time. When the characteristic address is updated, the data payload of the write operation is captured in parallel without suspending the main stream. Based on the hardware triggering mechanism, the data payload is synchronously directed to the corresponding address input terminal of the shadow register group; Based on the physical characteristics of dual-port registers, the dynamic configuration parameters are homomorphically stored in the shadow register group according to the strobe signal of the controller within the same clock cycle when the main register group is updated. After the mirroring is completed, the characteristic values of the master and mirror registers are checked for consistency through the built-in hardware comparison logic. After verification, a lock instruction is issued to put the shadow register group into read-only mode, and a context ready flag is sent to the pipeline's spy unit as a precondition for triggering subsequent verification signal injection.
3. The signal processing combined performance verification system based on DSP communication testing according to claim 1, characterized in that: In the empty slot injection module, the status registers of the main DSP core during the instruction fetch, decoding and execution stages are continuously monitored through the spy unit of the instruction pipeline, and pipeline pause signals and branch prediction failure flags are extracted to obtain the busy level of the main computing engine in real time. Using built-in hardware prediction logic, it predicts at the leading edge of the current instruction cycle whether there will be idle slots in the main computing unit waiting for external storage data or instruction synchronization in the next clock cycle. Once a specific vacant slot is identified, the combined verification controller immediately issues a computing power preemption command. By using a hardware multiplexer, the input of the computing engine can be temporarily switched to the data output of the shadow register group without severing the main path logical connection. At the beginning of the idle period, the shadow register group pushes the feature test vectors preset in the read-only memory to the computing engine in parallel according to the synchronized algorithm context, and completes the shadow operation on the feature test vectors. Intermediate and final results generated by the operation are directed to physically independent result buffers; One clock cycle before the idle slots expire, the shadow computing process is forcibly terminated and the computing engine access rights are released, achieving zero-latency verification that is perceived by the main business.
4. The signal processing combined performance verification system based on DSP communication testing according to claim 1, characterized in that: In the performance judgment module, the real-time business processing results are extracted from the main path by the combined verification controller, and the corresponding shadow operation results are extracted from the result buffer. The two sets of data are aligned at the algorithm logic level through internal clock alignment logic, eliminating time offset; The hardware comparison array performs the following metrics in parallel on the aligned data stream: calculates the Euclidean distance between the two sets of vectors to identify bit flips or hard computation errors; performs a fast Fourier transform on the equation output to extract the signal-to-noise ratio loss and out-of-band spurious distribution for evaluating numerical stability. The physical cycle from injection into an idle slot to result retrieval for each shadow operation is recorded using a high-precision timer, and the first and second derivatives of the response delay are calculated. Based on the preset system state weights, compound operations are performed using the built-in arithmetic logic unit.
5. The signal processing combined performance verification system based on DSP communication testing according to claim 4, characterized in that: The specific formula for performing the compound operation is as follows: ； wherein, represents a comprehensive performance factor, which is used to quantify the overall pros and cons of the DSP signal processing combination, represents an algorithm accuracy weight, represents a signal-to-noise ratio (SNR) drop value of the shadow path after processing the feature test vector, compared with the ideal error-free output, represents a theoretical SNR loss benchmark value of the same feature test vector processed by the same algorithm under ideal hardware conditions and an interference-free environment, represents a time determinacy weight, represents a second derivative of the response time delay; The output comprehensive performance factor is compared with a preset threshold array, and a scene determination is made based on the error between the main path and the shadow path. If the overall performance factor exceeds the threshold and the main path error is large while the shadow path error is small, it is determined that the service decline is caused by external electromagnetic interference. If the overall performance factor exceeds the threshold and both path errors are large, it is determined that the DSP's internal computing power is degraded or the context synchronization is abnormal. Based on the delimitation results, an interrupt signal is reported to the main control unit or a hot backup switch is triggered. 6.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is characterized in that: When the processor executes the computer program, it implements a module of the signal processing combined performance verification system based on DSP communication testing as described in any one of claims 1 to 4.
7. A computer readable storage medium having stored thereon a computer program, characterized in that: When the computer program is executed by the processor, it implements a module of the signal processing combined performance verification system based on DSP communication testing as described in any one of claims 1 to 4.