Compare Gate-All-Around Roughness for Enhanced Yield Simulation
APR 15, 20269 MIN READ
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Gate-All-Around Technology Background and Simulation Goals
Gate-All-Around (GAA) technology represents a revolutionary advancement in semiconductor device architecture, emerging as the successor to FinFET technology for advanced node manufacturing below 3nm. This three-dimensional transistor structure completely surrounds the channel with gate material, providing superior electrostatic control and enabling continued scaling of CMOS devices. The technology addresses critical challenges in short-channel effects, leakage current reduction, and performance enhancement that conventional planar and FinFET structures cannot adequately resolve at extreme scaling dimensions.
The evolution of GAA technology stems from the fundamental need to maintain Moore's Law progression while overcoming physical limitations of traditional transistor architectures. Unlike FinFET devices where the gate controls the channel from three sides, GAA structures achieve complete wraparound gate control, resulting in improved subthreshold swing, reduced drain-induced barrier lowering, and enhanced drive current capabilities. This architectural advantage becomes increasingly critical as device dimensions approach atomic scales.
Surface roughness in GAA devices presents unique challenges that significantly impact device performance and manufacturing yield. The increased surface area exposure in GAA structures amplifies the effects of interface roughness, making precise characterization and simulation of these variations essential for successful technology implementation. Roughness variations affect carrier mobility, threshold voltage uniformity, and overall device reliability, directly influencing production yield and economic viability.
Current simulation methodologies for GAA roughness analysis focus on developing comprehensive models that accurately capture the three-dimensional nature of surface variations and their impact on electrical characteristics. Advanced simulation frameworks must account for multiple roughness sources including gate sidewall roughness, channel surface roughness, and interface variations between different material layers. These simulations require sophisticated computational approaches that can handle the complex geometry and multi-physics interactions inherent in GAA structures.
The primary simulation goals encompass establishing robust predictive models for yield optimization, developing design guidelines for roughness tolerance, and creating manufacturing process windows that ensure consistent device performance. Enhanced simulation capabilities aim to reduce development cycles, minimize costly fabrication iterations, and enable proactive design optimization before physical prototyping. These objectives are crucial for successful GAA technology commercialization and maintaining competitive advantage in advanced semiconductor manufacturing.
The evolution of GAA technology stems from the fundamental need to maintain Moore's Law progression while overcoming physical limitations of traditional transistor architectures. Unlike FinFET devices where the gate controls the channel from three sides, GAA structures achieve complete wraparound gate control, resulting in improved subthreshold swing, reduced drain-induced barrier lowering, and enhanced drive current capabilities. This architectural advantage becomes increasingly critical as device dimensions approach atomic scales.
Surface roughness in GAA devices presents unique challenges that significantly impact device performance and manufacturing yield. The increased surface area exposure in GAA structures amplifies the effects of interface roughness, making precise characterization and simulation of these variations essential for successful technology implementation. Roughness variations affect carrier mobility, threshold voltage uniformity, and overall device reliability, directly influencing production yield and economic viability.
Current simulation methodologies for GAA roughness analysis focus on developing comprehensive models that accurately capture the three-dimensional nature of surface variations and their impact on electrical characteristics. Advanced simulation frameworks must account for multiple roughness sources including gate sidewall roughness, channel surface roughness, and interface variations between different material layers. These simulations require sophisticated computational approaches that can handle the complex geometry and multi-physics interactions inherent in GAA structures.
The primary simulation goals encompass establishing robust predictive models for yield optimization, developing design guidelines for roughness tolerance, and creating manufacturing process windows that ensure consistent device performance. Enhanced simulation capabilities aim to reduce development cycles, minimize costly fabrication iterations, and enable proactive design optimization before physical prototyping. These objectives are crucial for successful GAA technology commercialization and maintaining competitive advantage in advanced semiconductor manufacturing.
Market Demand for Advanced GAA Yield Simulation Tools
The semiconductor industry's transition to Gate-All-Around (GAA) transistor architectures has created substantial demand for sophisticated yield simulation tools capable of accurately modeling surface roughness effects. As traditional FinFET scaling approaches physical limitations, GAA structures represent the next frontier for advanced node development, driving unprecedented requirements for precision in manufacturing process simulation and yield optimization.
Manufacturing yield optimization has become increasingly critical as semiconductor fabrication costs escalate exponentially with each technology node advancement. The complexity of GAA structures, with their multiple nanowire or nanosheet channels surrounded by gate material, introduces new variability sources that conventional simulation tools struggle to address adequately. Surface roughness variations, particularly at the gate-channel interface, significantly impact device performance and yield, necessitating advanced simulation capabilities.
Electronic Design Automation (EDA) companies face growing pressure from semiconductor manufacturers to deliver simulation tools that can accurately predict yield impacts of GAA roughness variations. Major foundries require comprehensive modeling solutions to optimize their process flows and reduce manufacturing costs while maintaining competitive performance metrics. The ability to simulate and compare different roughness scenarios has become essential for process development and qualification.
The market demand extends beyond traditional semiconductor manufacturers to include fabless design companies, research institutions, and equipment suppliers. Design houses need accurate yield models to optimize their circuit designs for GAA processes, while equipment manufacturers require simulation feedback to improve their fabrication tools. Research organizations seek advanced simulation capabilities to explore novel GAA architectures and materials.
Current market dynamics indicate strong growth potential for GAA-specific simulation tools. The increasing adoption of GAA technology across multiple foundries creates a competitive environment where accurate yield prediction provides significant competitive advantages. Companies investing in advanced simulation capabilities can accelerate time-to-market for new processes and reduce development costs through improved first-pass success rates.
The demand for enhanced GAA yield simulation tools is further amplified by the industry's shift toward heterogeneous integration and advanced packaging technologies. These applications require precise understanding of device variability and yield characteristics to ensure reliable system-level performance. Simulation tools capable of modeling GAA roughness effects across different operating conditions and process variations have become indispensable for successful product development in this evolving landscape.
Manufacturing yield optimization has become increasingly critical as semiconductor fabrication costs escalate exponentially with each technology node advancement. The complexity of GAA structures, with their multiple nanowire or nanosheet channels surrounded by gate material, introduces new variability sources that conventional simulation tools struggle to address adequately. Surface roughness variations, particularly at the gate-channel interface, significantly impact device performance and yield, necessitating advanced simulation capabilities.
Electronic Design Automation (EDA) companies face growing pressure from semiconductor manufacturers to deliver simulation tools that can accurately predict yield impacts of GAA roughness variations. Major foundries require comprehensive modeling solutions to optimize their process flows and reduce manufacturing costs while maintaining competitive performance metrics. The ability to simulate and compare different roughness scenarios has become essential for process development and qualification.
The market demand extends beyond traditional semiconductor manufacturers to include fabless design companies, research institutions, and equipment suppliers. Design houses need accurate yield models to optimize their circuit designs for GAA processes, while equipment manufacturers require simulation feedback to improve their fabrication tools. Research organizations seek advanced simulation capabilities to explore novel GAA architectures and materials.
Current market dynamics indicate strong growth potential for GAA-specific simulation tools. The increasing adoption of GAA technology across multiple foundries creates a competitive environment where accurate yield prediction provides significant competitive advantages. Companies investing in advanced simulation capabilities can accelerate time-to-market for new processes and reduce development costs through improved first-pass success rates.
The demand for enhanced GAA yield simulation tools is further amplified by the industry's shift toward heterogeneous integration and advanced packaging technologies. These applications require precise understanding of device variability and yield characteristics to ensure reliable system-level performance. Simulation tools capable of modeling GAA roughness effects across different operating conditions and process variations have become indispensable for successful product development in this evolving landscape.
Current GAA Roughness Modeling Challenges and Limitations
Current Gate-All-Around (GAA) roughness modeling faces significant computational and accuracy challenges that limit its effectiveness in yield simulation applications. Traditional modeling approaches struggle to capture the complex three-dimensional nature of surface roughness variations in GAA transistors, particularly at the nanoscale dimensions where quantum effects become prominent. The cylindrical or sheet-like geometry of GAA structures introduces unique roughness characteristics that differ substantially from conventional FinFET or planar devices.
Existing simulation tools often rely on simplified statistical models that fail to account for the spatial correlation of roughness patterns along the channel length and around the gate circumference. These limitations become particularly problematic when attempting to predict device-to-device variations and their impact on circuit-level performance. The lack of comprehensive experimental data for model validation further compounds these challenges, as direct measurement of nanoscale roughness in GAA structures remains technically demanding.
Current modeling frameworks typically employ Gaussian or exponential correlation functions to describe roughness behavior, but these approaches inadequately represent the actual physical mechanisms governing surface formation during manufacturing processes. The interaction between line edge roughness (LER) and line width roughness (LWR) in GAA geometries creates complex coupling effects that are poorly captured by existing analytical models. This results in significant discrepancies between simulated and measured device characteristics.
Computational efficiency presents another major limitation, as accurate roughness modeling requires extremely fine mesh resolution and extensive Monte Carlo sampling to achieve statistical significance. The computational burden becomes prohibitive when scaling to full-chip yield analysis, forcing engineers to make compromises between accuracy and simulation time. Additionally, the lack of standardized roughness characterization metrics across different GAA architectures hampers the development of universal modeling approaches.
Process-induced variations in GAA fabrication, including selective etching and epitaxial growth steps, introduce roughness patterns that are not adequately addressed by current modeling methodologies. The multi-step nature of GAA processing creates layer-dependent roughness characteristics that require sophisticated modeling techniques to capture accurately. These limitations collectively restrict the reliability of yield predictions and optimization strategies for GAA-based technologies.
Existing simulation tools often rely on simplified statistical models that fail to account for the spatial correlation of roughness patterns along the channel length and around the gate circumference. These limitations become particularly problematic when attempting to predict device-to-device variations and their impact on circuit-level performance. The lack of comprehensive experimental data for model validation further compounds these challenges, as direct measurement of nanoscale roughness in GAA structures remains technically demanding.
Current modeling frameworks typically employ Gaussian or exponential correlation functions to describe roughness behavior, but these approaches inadequately represent the actual physical mechanisms governing surface formation during manufacturing processes. The interaction between line edge roughness (LER) and line width roughness (LWR) in GAA geometries creates complex coupling effects that are poorly captured by existing analytical models. This results in significant discrepancies between simulated and measured device characteristics.
Computational efficiency presents another major limitation, as accurate roughness modeling requires extremely fine mesh resolution and extensive Monte Carlo sampling to achieve statistical significance. The computational burden becomes prohibitive when scaling to full-chip yield analysis, forcing engineers to make compromises between accuracy and simulation time. Additionally, the lack of standardized roughness characterization metrics across different GAA architectures hampers the development of universal modeling approaches.
Process-induced variations in GAA fabrication, including selective etching and epitaxial growth steps, introduce roughness patterns that are not adequately addressed by current modeling methodologies. The multi-step nature of GAA processing creates layer-dependent roughness characteristics that require sophisticated modeling techniques to capture accurately. These limitations collectively restrict the reliability of yield predictions and optimization strategies for GAA-based technologies.
Existing GAA Roughness Simulation Solutions
01 Gate-All-Around transistor structure design and fabrication
Gate-All-Around (GAA) transistors feature a gate structure that completely surrounds the channel region, providing superior electrostatic control compared to conventional planar devices. The fabrication process involves forming nanowire or nanosheet channels with the gate material wrapping around all sides. This architecture enables better short-channel effect control and improved device scalability for advanced semiconductor nodes.- Gate-All-Around transistor structure design and fabrication: Gate-All-Around (GAA) transistors feature a gate structure that completely surrounds the channel region, providing improved electrostatic control and reduced short-channel effects. The fabrication process involves forming nanowire or nanosheet channels with gate material wrapping around all sides. This architecture enables better performance scaling and reduced leakage current compared to conventional FinFET structures.
- Surface roughness control in GAA channel formation: Surface roughness at the channel-gate interface significantly impacts carrier mobility and device performance in GAA transistors. Techniques for controlling roughness include optimized etching processes, thermal treatments, and selective epitaxial growth methods. Smooth channel surfaces reduce scattering effects and improve electrical characteristics. Process parameters such as temperature, pressure, and chemical composition are carefully controlled to minimize surface irregularities.
- Line edge roughness and line width roughness mitigation: Line edge roughness (LER) and line width roughness (LWR) are critical concerns in GAA device patterning that affect device uniformity and performance variability. Advanced lithography techniques, resist materials, and pattern transfer methods are employed to reduce these roughness variations. Post-patterning treatments including smoothing processes and atomic layer deposition can further improve edge definition and reduce dimensional variations.
- Gate dielectric interface roughness optimization: The interface between the gate dielectric and channel in GAA structures requires careful roughness management to ensure reliable device operation and minimize threshold voltage variations. Deposition techniques such as atomic layer deposition provide conformal coverage with controlled interface quality. Surface preparation methods including cleaning and passivation steps help achieve smooth interfaces. The roughness at this critical interface directly influences gate capacitance and charge trapping behavior.
- Measurement and characterization of GAA roughness: Accurate measurement and characterization of surface roughness in GAA structures is essential for process control and device optimization. Techniques include atomic force microscopy, transmission electron microscopy, and scatterometry for assessing roughness at various stages of fabrication. Statistical analysis methods quantify roughness parameters and correlate them with electrical performance. In-line monitoring enables feedback control for maintaining target roughness specifications throughout manufacturing.
02 Surface roughness control in GAA channel formation
Surface roughness at the channel-gate interface significantly impacts carrier mobility and device performance in GAA structures. Techniques to minimize roughness include optimized etching processes, controlled oxidation and removal cycles, and selective epitaxial growth methods. Smooth channel surfaces reduce scattering effects and improve electrical characteristics such as transconductance and threshold voltage uniformity.Expand Specific Solutions03 Gate dielectric deposition and interface quality
The gate dielectric layer in GAA devices must conformally coat the three-dimensional channel structure while maintaining uniform thickness and minimal interface defects. Advanced deposition techniques such as atomic layer deposition ensure complete coverage around nanowire or nanosheet channels. Interface roughness between the channel and dielectric directly affects charge carrier transport and device reliability.Expand Specific Solutions04 Line edge roughness and pattern transfer optimization
Line edge roughness (LER) during lithography and pattern transfer processes can propagate into the final GAA structure, affecting channel dimensions and electrical uniformity. Advanced lithography techniques, improved resist materials, and optimized etch chemistries help minimize LER. Controlling pattern roughness is critical for achieving consistent device performance across large-scale integration.Expand Specific Solutions05 Measurement and characterization of GAA surface morphology
Accurate characterization of surface roughness in GAA structures requires advanced metrology techniques including atomic force microscopy, transmission electron microscopy, and scatterometry. These methods enable quantification of roughness parameters at nanoscale dimensions. Understanding the relationship between measured roughness and electrical performance guides process optimization and quality control in GAA device manufacturing.Expand Specific Solutions
Key Players in GAA Simulation and EDA Industry
The Gate-All-Around (GAA) roughness simulation technology represents a critical advancement in semiconductor manufacturing, particularly as the industry transitions to sub-3nm process nodes. The competitive landscape is dominated by established foundry leaders including TSMC, Samsung Electronics, and GLOBALFOUNDRIES, who are driving technology maturity through advanced FinFET and GAA implementations. Chinese players like SMIC and Shanghai Huali are rapidly developing capabilities, while EDA companies such as Siemens Industry Software provide essential simulation tools. The market is experiencing significant growth driven by AI, 5G, and automotive semiconductor demands. Technology maturity varies considerably, with TSMC and Samsung leading in 3nm GAA production readiness, while other foundries are in various development stages. Research institutions like Tsinghua University and Beijing Institute of Technology contribute fundamental research, indicating strong academic-industry collaboration in advancing yield simulation methodologies for next-generation transistor architectures.
Taiwan Semiconductor Manufacturing Co., Ltd.
Technical Solution: TSMC has developed comprehensive Gate-All-Around (GAA) roughness characterization and yield simulation methodologies for their advanced 3nm and 2nm process nodes. Their approach integrates statistical process variation modeling with Monte Carlo simulations to predict yield impacts from line edge roughness (LER) and line width roughness (LWR) in GAA nanosheet transistors. The company employs advanced metrology tools including critical dimension scanning electron microscopy (CD-SEM) and atomic force microscopy (AFM) to measure roughness parameters across multiple gate fingers. Their simulation framework incorporates physics-based models that correlate roughness-induced threshold voltage variations with device performance metrics, enabling accurate yield predictions for high-volume manufacturing.
Strengths: Industry-leading manufacturing experience and advanced process control capabilities. Weaknesses: High development costs and complex integration challenges for new roughness mitigation techniques.
GLOBALFOUNDRIES, Inc.
Technical Solution: GlobalFoundries has developed a comprehensive GAA roughness characterization framework that emphasizes statistical process control and yield optimization for their advanced FinFET-to-GAA transition roadmap. Their approach utilizes inline metrology systems combined with offline analytical techniques to quantify surface roughness parameters including power spectral density (PSD) analysis and correlation function modeling. The company's simulation methodology incorporates variability-aware design techniques that account for both systematic and random roughness components in GAA structures. Their yield prediction models integrate process-induced variations with device-level performance metrics, enabling early identification of yield-limiting factors and optimization of manufacturing processes for enhanced production efficiency.
Strengths: Extensive foundry experience and focus on yield optimization methodologies. Weaknesses: Technology node limitations compared to leading competitors and resource constraints for advanced R&D.
Core Innovations in GAA Roughness Yield Modeling
Method for fabricating gate-all-around (GAA) structure
PatentPendingUS20230387249A1
Innovation
- A method is developed to reduce the aspect ratio of the dummy gate by selective epitaxy growth of a SiGe layer and chemical mechanical polishing (CMP) to form a SiGe stacked structure, followed by patterning and etching processes that minimize damage and improve uniformity, reducing parasitic capacitance through the use of epitaxial SiGe for all-around gates.
Gate-All-Around Device with Protective Dielectric Layer and Method of Forming the Same
PatentActiveUS20240250142A1
Innovation
- A protective dielectric layer is disposed over the topmost channel semiconductor layer to prevent damage during dummy gate etching, and is used as a stop layer to ensure uniform metal gate profiles, allowing for consistent threshold voltage across different channel semiconductor layers.
Semiconductor Manufacturing Standards for GAA
The semiconductor industry has established comprehensive manufacturing standards specifically tailored for Gate-All-Around (GAA) transistor architectures to address the unique challenges posed by their three-dimensional structure. These standards encompass critical dimensional control, surface roughness specifications, and process uniformity requirements that directly impact device performance and manufacturing yield.
International standards organizations, including SEMI and IEEE, have developed specific guidelines for GAA device fabrication that emphasize nanowire and nanosheet dimensional accuracy. The standards define acceptable tolerances for critical dimensions such as channel width, thickness uniformity, and sidewall verticality. Surface roughness parameters are particularly stringent, with line edge roughness (LER) and line width roughness (LWR) specifications typically requiring sub-nanometer precision to ensure consistent electrical characteristics across the wafer.
Process control standards for GAA manufacturing focus on multi-step lithography alignment, etch selectivity requirements, and epitaxial growth uniformity. The standards mandate specific metrology protocols for in-line monitoring of nanowire formation, including cross-sectional analysis and three-dimensional profiling techniques. Quality control checkpoints are established at each critical process step, from initial silicon fin formation through final gate wrap-around completion.
Material purity and contamination control standards are exceptionally rigorous for GAA processes due to the increased surface area exposure during fabrication. The standards specify maximum allowable particle counts, metallic contamination levels, and organic residue limits that are significantly tighter than conventional planar device requirements. Clean room protocols and equipment qualification procedures are enhanced to accommodate the extended process sequences typical in GAA manufacturing.
Electrical testing standards for GAA devices incorporate specialized measurement techniques to characterize the unique transport properties of wrapped-gate structures. These include specific protocols for threshold voltage uniformity assessment, subthreshold slope measurement, and short-channel effect evaluation. The standards also define statistical sampling methodologies and acceptance criteria that account for the inherent variability challenges in three-dimensional device architectures, ensuring robust yield prediction and process optimization capabilities.
International standards organizations, including SEMI and IEEE, have developed specific guidelines for GAA device fabrication that emphasize nanowire and nanosheet dimensional accuracy. The standards define acceptable tolerances for critical dimensions such as channel width, thickness uniformity, and sidewall verticality. Surface roughness parameters are particularly stringent, with line edge roughness (LER) and line width roughness (LWR) specifications typically requiring sub-nanometer precision to ensure consistent electrical characteristics across the wafer.
Process control standards for GAA manufacturing focus on multi-step lithography alignment, etch selectivity requirements, and epitaxial growth uniformity. The standards mandate specific metrology protocols for in-line monitoring of nanowire formation, including cross-sectional analysis and three-dimensional profiling techniques. Quality control checkpoints are established at each critical process step, from initial silicon fin formation through final gate wrap-around completion.
Material purity and contamination control standards are exceptionally rigorous for GAA processes due to the increased surface area exposure during fabrication. The standards specify maximum allowable particle counts, metallic contamination levels, and organic residue limits that are significantly tighter than conventional planar device requirements. Clean room protocols and equipment qualification procedures are enhanced to accommodate the extended process sequences typical in GAA manufacturing.
Electrical testing standards for GAA devices incorporate specialized measurement techniques to characterize the unique transport properties of wrapped-gate structures. These include specific protocols for threshold voltage uniformity assessment, subthreshold slope measurement, and short-channel effect evaluation. The standards also define statistical sampling methodologies and acceptance criteria that account for the inherent variability challenges in three-dimensional device architectures, ensuring robust yield prediction and process optimization capabilities.
Process Variation Impact on GAA Device Performance
Process variations in semiconductor manufacturing significantly impact Gate-All-Around (GAA) device performance, creating substantial challenges for yield optimization and device reliability. These variations manifest across multiple dimensions, including geometric fluctuations, material property deviations, and processing parameter inconsistencies that collectively influence the electrical characteristics of GAA transistors.
Geometric variations represent the most critical factor affecting GAA device performance. Line width roughness (LWR) and line edge roughness (LER) directly alter the effective channel width and gate control efficiency. In GAA structures, where the gate completely surrounds the channel, even minor geometric deviations can lead to significant threshold voltage shifts and mobility degradation. The three-dimensional nature of GAA devices amplifies these effects compared to traditional planar transistors.
Material property variations, particularly in the high-k dielectric and metal gate stack, introduce additional performance uncertainties. Work function variations in metal gates can cause threshold voltage fluctuations exceeding 50mV in advanced nodes. Interface trap density variations between the channel material and gate dielectric further contribute to performance dispersion, affecting both DC characteristics and reliability metrics.
Processing parameter fluctuations during critical manufacturing steps compound these challenges. Temperature variations during annealing processes can alter dopant activation and interface quality. Etch process variations affect the uniformity of channel release and gate formation, leading to device-to-device performance variations within the same wafer.
The statistical nature of these variations requires sophisticated modeling approaches to predict their cumulative impact on circuit performance. Monte Carlo simulations incorporating correlated variation sources provide insights into yield sensitivities and performance distributions. Understanding the interaction between different variation sources enables the development of design-for-manufacturing strategies that improve yield while maintaining performance targets.
Advanced characterization techniques, including electrical parameter extraction and physical analysis, reveal the correlation between specific process variations and resulting device performance metrics. This understanding facilitates the development of process control strategies and design optimization methodologies for enhanced GAA device manufacturing yield.
Geometric variations represent the most critical factor affecting GAA device performance. Line width roughness (LWR) and line edge roughness (LER) directly alter the effective channel width and gate control efficiency. In GAA structures, where the gate completely surrounds the channel, even minor geometric deviations can lead to significant threshold voltage shifts and mobility degradation. The three-dimensional nature of GAA devices amplifies these effects compared to traditional planar transistors.
Material property variations, particularly in the high-k dielectric and metal gate stack, introduce additional performance uncertainties. Work function variations in metal gates can cause threshold voltage fluctuations exceeding 50mV in advanced nodes. Interface trap density variations between the channel material and gate dielectric further contribute to performance dispersion, affecting both DC characteristics and reliability metrics.
Processing parameter fluctuations during critical manufacturing steps compound these challenges. Temperature variations during annealing processes can alter dopant activation and interface quality. Etch process variations affect the uniformity of channel release and gate formation, leading to device-to-device performance variations within the same wafer.
The statistical nature of these variations requires sophisticated modeling approaches to predict their cumulative impact on circuit performance. Monte Carlo simulations incorporating correlated variation sources provide insights into yield sensitivities and performance distributions. Understanding the interaction between different variation sources enables the development of design-for-manufacturing strategies that improve yield while maintaining performance targets.
Advanced characterization techniques, including electrical parameter extraction and physical analysis, reveal the correlation between specific process variations and resulting device performance metrics. This understanding facilitates the development of process control strategies and design optimization methodologies for enhanced GAA device manufacturing yield.
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