How to Enhance AI Processing Techniques with Wafer-Scale Engines
APR 15, 20268 MIN READ
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Wafer-Scale AI Engine Development Background and Objectives
The evolution of artificial intelligence processing has reached a critical juncture where traditional computing architectures face fundamental limitations in meeting the exponential demands of modern AI workloads. Conventional processors, designed for sequential operations, struggle with the massively parallel nature of neural network computations, creating bottlenecks that impede the advancement of AI applications across industries.
Wafer-scale AI engines represent a paradigm shift in computing architecture, emerging from the recognition that AI processing requires fundamentally different design principles. Unlike traditional chip-based systems that rely on multiple discrete processors connected through complex interconnects, wafer-scale engines utilize an entire silicon wafer as a single, unified computing platform. This approach eliminates many of the communication delays and bandwidth limitations that plague conventional distributed systems.
The historical trajectory of AI processing has consistently pushed against the boundaries of available computing power. From early neural networks running on general-purpose CPUs to specialized graphics processing units and tensor processing units, each advancement has sought to better align hardware capabilities with AI computational patterns. Wafer-scale engines represent the next logical step in this evolution, offering unprecedented scale and efficiency for AI workloads.
The primary objective of wafer-scale AI engine development centers on achieving breakthrough performance improvements in training and inference tasks for large-scale neural networks. These systems aim to support models with trillions of parameters while maintaining energy efficiency and reducing the time-to-solution for complex AI problems. The technology targets applications ranging from natural language processing and computer vision to scientific computing and autonomous systems.
Key technical objectives include maximizing on-chip memory capacity to reduce external data movement, implementing high-bandwidth interconnects between processing elements, and developing fault-tolerance mechanisms to handle inevitable defects across large silicon areas. The ultimate goal is creating a computing substrate that can scale AI capabilities beyond current limitations while establishing new benchmarks for performance per watt and total computational throughput in artificial intelligence applications.
Wafer-scale AI engines represent a paradigm shift in computing architecture, emerging from the recognition that AI processing requires fundamentally different design principles. Unlike traditional chip-based systems that rely on multiple discrete processors connected through complex interconnects, wafer-scale engines utilize an entire silicon wafer as a single, unified computing platform. This approach eliminates many of the communication delays and bandwidth limitations that plague conventional distributed systems.
The historical trajectory of AI processing has consistently pushed against the boundaries of available computing power. From early neural networks running on general-purpose CPUs to specialized graphics processing units and tensor processing units, each advancement has sought to better align hardware capabilities with AI computational patterns. Wafer-scale engines represent the next logical step in this evolution, offering unprecedented scale and efficiency for AI workloads.
The primary objective of wafer-scale AI engine development centers on achieving breakthrough performance improvements in training and inference tasks for large-scale neural networks. These systems aim to support models with trillions of parameters while maintaining energy efficiency and reducing the time-to-solution for complex AI problems. The technology targets applications ranging from natural language processing and computer vision to scientific computing and autonomous systems.
Key technical objectives include maximizing on-chip memory capacity to reduce external data movement, implementing high-bandwidth interconnects between processing elements, and developing fault-tolerance mechanisms to handle inevitable defects across large silicon areas. The ultimate goal is creating a computing substrate that can scale AI capabilities beyond current limitations while establishing new benchmarks for performance per watt and total computational throughput in artificial intelligence applications.
Market Demand for Large-Scale AI Processing Solutions
The global artificial intelligence market is experiencing unprecedented growth, driven by the exponential increase in computational demands across multiple sectors. Traditional computing architectures are reaching their limits in handling the massive parallel processing requirements of modern AI workloads, creating a significant market opportunity for revolutionary processing solutions.
Enterprise demand for large-scale AI processing capabilities spans diverse industries including autonomous vehicles, natural language processing, computer vision, and scientific computing. Data centers worldwide are struggling with the computational bottlenecks imposed by conventional GPU clusters and distributed computing systems, particularly when dealing with large language models and complex neural networks that require extensive memory bandwidth and processing power.
The emergence of wafer-scale computing represents a paradigm shift in addressing these computational challenges. Organizations are increasingly seeking solutions that can handle trillion-parameter models and real-time inference at scale, driving demand for processing architectures that eliminate traditional chip-to-chip communication bottlenecks and memory limitations.
Cloud service providers and hyperscale data centers constitute the primary market segment, requiring processing solutions that can deliver superior performance per watt while reducing infrastructure complexity. The growing adoption of edge AI applications further amplifies demand for efficient large-scale processing capabilities that can be deployed across distributed computing environments.
Research institutions and academic organizations represent another significant market segment, particularly those engaged in scientific computing, climate modeling, and advanced AI research. These entities require processing capabilities that can accelerate training times for complex models while maintaining cost-effectiveness for extended computational workloads.
The market demand is further intensified by the competitive landscape in AI development, where organizations seek technological advantages through superior processing capabilities. Companies developing autonomous systems, recommendation engines, and real-time AI applications are actively pursuing processing solutions that can provide substantial performance improvements over existing architectures, creating a robust market foundation for wafer-scale processing innovations.
Enterprise demand for large-scale AI processing capabilities spans diverse industries including autonomous vehicles, natural language processing, computer vision, and scientific computing. Data centers worldwide are struggling with the computational bottlenecks imposed by conventional GPU clusters and distributed computing systems, particularly when dealing with large language models and complex neural networks that require extensive memory bandwidth and processing power.
The emergence of wafer-scale computing represents a paradigm shift in addressing these computational challenges. Organizations are increasingly seeking solutions that can handle trillion-parameter models and real-time inference at scale, driving demand for processing architectures that eliminate traditional chip-to-chip communication bottlenecks and memory limitations.
Cloud service providers and hyperscale data centers constitute the primary market segment, requiring processing solutions that can deliver superior performance per watt while reducing infrastructure complexity. The growing adoption of edge AI applications further amplifies demand for efficient large-scale processing capabilities that can be deployed across distributed computing environments.
Research institutions and academic organizations represent another significant market segment, particularly those engaged in scientific computing, climate modeling, and advanced AI research. These entities require processing capabilities that can accelerate training times for complex models while maintaining cost-effectiveness for extended computational workloads.
The market demand is further intensified by the competitive landscape in AI development, where organizations seek technological advantages through superior processing capabilities. Companies developing autonomous systems, recommendation engines, and real-time AI applications are actively pursuing processing solutions that can provide substantial performance improvements over existing architectures, creating a robust market foundation for wafer-scale processing innovations.
Current State and Challenges of Wafer-Scale AI Computing
Wafer-scale AI computing represents a paradigm shift from traditional chip-based architectures to massive, single-wafer processors designed specifically for artificial intelligence workloads. Currently, Cerebras Systems leads this domain with their Wafer-Scale Engine (WSE) series, featuring hundreds of thousands of processing cores interconnected on a single silicon wafer. This approach eliminates traditional memory bandwidth bottlenecks and inter-chip communication delays that plague conventional GPU clusters.
The current technological landscape shows promising developments in fabrication techniques and architectural innovations. Advanced semiconductor manufacturing processes at 7nm and below enable the integration of massive core counts while maintaining acceptable yield rates. Modern wafer-scale designs incorporate sophisticated fault tolerance mechanisms, allowing systems to function effectively even with a percentage of defective cores distributed across the wafer surface.
However, significant technical challenges persist in this emerging field. Thermal management remains the most critical obstacle, as dissipating heat uniformly across an entire wafer requires revolutionary cooling solutions beyond conventional air or liquid cooling systems. Power distribution presents another fundamental challenge, demanding innovative approaches to deliver stable power to hundreds of thousands of cores while minimizing voltage drops and electromagnetic interference.
Manufacturing yield optimization continues to constrain commercial viability. Unlike traditional chips where defective units can be discarded, wafer-scale processors must incorporate redundancy and reconfiguration capabilities to work around inevitable manufacturing defects. This requirement adds complexity to both hardware design and software stack development.
Software ecosystem maturity represents a substantial barrier to widespread adoption. Current programming models and development tools are primarily designed for conventional multi-core or GPU architectures. Adapting existing AI frameworks and developing new programming paradigms that can effectively utilize the massive parallelism of wafer-scale systems requires significant investment and time.
Cost considerations also limit market penetration. The economics of wafer-scale manufacturing differ dramatically from traditional semiconductor production, with higher upfront costs and specialized packaging requirements. Additionally, the infrastructure needed to support these systems, including power delivery and cooling, represents substantial capital expenditure for potential adopters.
Despite these challenges, recent advances in chiplet architectures and advanced packaging technologies are creating new pathways for wafer-scale integration. Emerging solutions in photonic interconnects and novel cooling methodologies show potential for addressing current limitations, suggesting that wafer-scale AI computing may overcome existing barriers within the next technological generation.
The current technological landscape shows promising developments in fabrication techniques and architectural innovations. Advanced semiconductor manufacturing processes at 7nm and below enable the integration of massive core counts while maintaining acceptable yield rates. Modern wafer-scale designs incorporate sophisticated fault tolerance mechanisms, allowing systems to function effectively even with a percentage of defective cores distributed across the wafer surface.
However, significant technical challenges persist in this emerging field. Thermal management remains the most critical obstacle, as dissipating heat uniformly across an entire wafer requires revolutionary cooling solutions beyond conventional air or liquid cooling systems. Power distribution presents another fundamental challenge, demanding innovative approaches to deliver stable power to hundreds of thousands of cores while minimizing voltage drops and electromagnetic interference.
Manufacturing yield optimization continues to constrain commercial viability. Unlike traditional chips where defective units can be discarded, wafer-scale processors must incorporate redundancy and reconfiguration capabilities to work around inevitable manufacturing defects. This requirement adds complexity to both hardware design and software stack development.
Software ecosystem maturity represents a substantial barrier to widespread adoption. Current programming models and development tools are primarily designed for conventional multi-core or GPU architectures. Adapting existing AI frameworks and developing new programming paradigms that can effectively utilize the massive parallelism of wafer-scale systems requires significant investment and time.
Cost considerations also limit market penetration. The economics of wafer-scale manufacturing differ dramatically from traditional semiconductor production, with higher upfront costs and specialized packaging requirements. Additionally, the infrastructure needed to support these systems, including power delivery and cooling, represents substantial capital expenditure for potential adopters.
Despite these challenges, recent advances in chiplet architectures and advanced packaging technologies are creating new pathways for wafer-scale integration. Emerging solutions in photonic interconnects and novel cooling methodologies show potential for addressing current limitations, suggesting that wafer-scale AI computing may overcome existing barriers within the next technological generation.
Existing Wafer-Scale AI Processing Solutions
01 Wafer-scale integration architecture for AI processing
Wafer-scale integration involves designing and manufacturing AI processing systems at the wafer level rather than individual chip level. This approach enables massive parallelism and interconnectivity across the entire wafer surface, allowing for enhanced computational capabilities. The architecture typically includes distributed processing elements, high-bandwidth interconnects, and specialized memory hierarchies optimized for AI workloads. This technique significantly reduces communication latency between processing units and improves overall system performance for large-scale neural network computations.- Wafer-scale integration architecture for AI processing: Wafer-scale engines utilize integrated circuit architectures that span entire semiconductor wafers rather than individual chips. This approach enables massive parallelism and interconnectivity for AI workloads by eliminating traditional chip boundaries. The architecture incorporates specialized processing elements distributed across the wafer surface, enabling efficient data flow and reduced latency for neural network computations. Advanced packaging techniques and thermal management solutions are employed to maintain operational stability across the large-scale integrated system.
- Neural network acceleration using wafer-scale processors: Specialized hardware implementations optimize neural network operations including convolution, matrix multiplication, and activation functions across wafer-scale architectures. These systems employ distributed memory hierarchies and optimized data paths to accelerate deep learning inference and training. The processing techniques include pipelined execution, parallel computation units, and efficient weight distribution mechanisms that leverage the massive connectivity available in wafer-scale designs.
- Interconnect and communication protocols for wafer-scale AI systems: Advanced interconnection schemes enable efficient data transfer between processing elements distributed across wafer-scale engines. These protocols support high-bandwidth, low-latency communication necessary for AI workloads, including gradient synchronization and parameter updates. The communication architecture incorporates mesh networks, routing algorithms, and flow control mechanisms optimized for the unique topology of wafer-scale integration.
- Fault tolerance and yield optimization in wafer-scale AI processors: Manufacturing techniques and architectural strategies address the challenge of defects across large wafer-scale integrated systems. Redundancy mechanisms, reconfiguration capabilities, and defect mapping enable functional operation despite manufacturing imperfections. These approaches include spare processing elements, adaptive routing, and testing methodologies that identify and isolate faulty components while maintaining overall system performance for AI applications.
- Power management and thermal control for wafer-scale AI engines: Specialized power distribution networks and thermal management systems address the unique challenges of operating high-performance AI processors at wafer scale. These techniques include dynamic voltage and frequency scaling, localized power gating, and advanced cooling solutions. The power management strategies optimize energy efficiency while maintaining computational throughput, incorporating monitoring systems that track power consumption and temperature across the wafer surface.
02 Neural network acceleration using wafer-scale hardware
Specialized hardware implementations on wafer-scale platforms enable efficient execution of neural network operations. These systems incorporate dedicated processing units optimized for matrix multiplications, convolutions, and activation functions commonly used in deep learning. The wafer-scale approach allows for massive parallel execution of neural network layers with minimal data movement overhead. Advanced techniques include dataflow architectures, systolic arrays, and specialized memory access patterns that maximize throughput for training and inference tasks.Expand Specific Solutions03 Distributed memory and data management in wafer-scale systems
Effective memory architecture is crucial for wafer-scale AI processing systems. These implementations feature hierarchical memory structures with local caches, shared memory regions, and global memory spaces distributed across the wafer. Advanced data management techniques include intelligent prefetching, data replication strategies, and coherence protocols optimized for AI workloads. The memory system is designed to minimize data movement and maximize bandwidth utilization, supporting the high computational demands of modern AI applications.Expand Specific Solutions04 Thermal management and power distribution for wafer-scale AI engines
Wafer-scale AI processing systems require sophisticated thermal management and power delivery solutions due to their high power density. These systems incorporate advanced cooling mechanisms, thermal monitoring sensors, and dynamic power management techniques. The power distribution network is designed to handle high current demands while maintaining voltage stability across the entire wafer. Techniques include localized power gating, adaptive voltage scaling, and thermal-aware workload scheduling to optimize performance while preventing hotspots and ensuring reliable operation.Expand Specific Solutions05 Fault tolerance and yield optimization in wafer-scale manufacturing
Manufacturing wafer-scale AI processors presents unique challenges in terms of defect management and yield optimization. These systems implement redundancy mechanisms, defect mapping, and reconfiguration capabilities to maintain functionality despite manufacturing imperfections. Techniques include spare processing elements, adaptive routing around defective regions, and error correction mechanisms. The design incorporates testing and diagnostic features that enable identification and isolation of faulty components, allowing the system to operate at reduced capacity rather than complete failure.Expand Specific Solutions
Key Players in Wafer-Scale AI Engine Industry
The wafer-scale AI processing engine market represents an emerging technological frontier currently in its early development stage, with significant growth potential driven by increasing demand for high-performance AI computing solutions. The market remains relatively nascent but shows promising expansion as organizations seek to overcome traditional computing bottlenecks. Technology maturity varies considerably across key players, with established semiconductor giants like Intel, Samsung Electronics, and Applied Materials leveraging decades of wafer fabrication expertise, while specialized companies such as TetraMem focus on innovative analog in-memory computing architectures. Chinese players including Huawei Technologies and Shanghai Tianshu Zhixin are rapidly advancing their capabilities, alongside traditional foundries like GlobalFoundries. Research institutions like MIT and the Institute of Computing Technology are contributing fundamental breakthroughs, creating a competitive landscape where manufacturing scale, technological innovation, and specialized AI optimization capabilities determine market positioning in this transformative sector.
Huawei Technologies Co., Ltd.
Technical Solution: Huawei has developed wafer-scale AI processing solutions through their Ascend AI chip architecture scaled to wafer-level integration. Their approach combines thousands of AI processing cores with advanced interconnect networks optimized for neural network computations. Huawei's wafer-scale engines utilize their self-developed Da Vinci architecture cores arranged in mesh topologies across the wafer surface. The company's solution incorporates advanced compiler technologies and software stacks that can efficiently map AI workloads across the distributed processing elements, enabling seamless scaling from edge devices to data center applications.
Strengths: Integrated hardware-software co-design and strong AI algorithm optimization. Weaknesses: Limited access to advanced manufacturing nodes due to trade restrictions and reduced ecosystem support in some markets.
Samsung Electronics Co., Ltd.
Technical Solution: Samsung has developed wafer-scale AI processing solutions that leverage their advanced semiconductor manufacturing capabilities and memory technologies. Their approach integrates high-bandwidth memory (HBM) directly with AI processing cores at the wafer level, creating memory-centric computing architectures. Samsung's wafer-scale engines utilize advanced packaging technologies including fan-out wafer-level packaging (FOWLP) and 2.5D/3D integration to achieve high compute density. The company's solution incorporates neuromorphic computing elements and in-memory computing capabilities that enable efficient AI inference and training across large-scale neural networks.
Strengths: Leading memory technology integration and advanced manufacturing processes. Weaknesses: Less focus on AI-specific architectures compared to pure-play AI companies and higher manufacturing complexity.
Core Innovations in Wafer-Scale AI Architecture Design
Active Wafer-Scale Reconfigurable Logic Fabric for AI and High-Performance Embedded Computing
PatentPendingUS20250159983A1
Innovation
- A novel active and passive wafer-scale fabric that integrates hundreds of closely-spaced bare-die chips, such as memory, GPUs, FPGAs, and AI accelerators, into a single wafer, enabling higher bandwidth and lower connectivity loss through reconfigurable logic fabrics and micro-bump integration.
Wafer calculator and method of fabricating wafer calculator
PatentPendingEP4571581A1
Innovation
- A wafer calculator is designed with processing elements having dedicated semiconductor patterns for specific partial areas of an AI model and routing elements providing communication paths according to the AI model's network structure, forming a stacked structure with separate wafers for processing and routing elements.
Manufacturing Yield Optimization for Wafer-Scale Engines
Manufacturing yield optimization represents one of the most critical challenges in wafer-scale engine production, directly impacting the commercial viability and scalability of AI processing systems. Unlike traditional semiconductor manufacturing where defective chips can be discarded individually, wafer-scale engines require the entire wafer to function as a cohesive processing unit, making yield optimization paramount to economic feasibility.
The fundamental challenge stems from the statistical nature of semiconductor defects across large silicon areas. Traditional chip manufacturing achieves acceptable yields by producing hundreds of smaller dies per wafer, where individual defective units can be rejected without affecting others. However, wafer-scale engines encompass the entire wafer surface, meaning any critical defect could potentially compromise the entire system's functionality.
Advanced defect tolerance mechanisms have emerged as primary solutions to address yield challenges. These include redundant processing elements distributed across the wafer surface, allowing the system to bypass defective cores while maintaining overall computational capacity. Dynamic reconfiguration capabilities enable real-time mapping around faulty regions, ensuring continued operation despite localized failures.
Process control optimization plays a crucial role in maximizing manufacturing yields. Enhanced lithography techniques, improved chemical mechanical planarization, and advanced metrology systems help reduce defect density across the wafer surface. Statistical process control methods enable manufacturers to identify and correct variations before they impact yield rates significantly.
Innovative design-for-manufacturability approaches specifically tailored for wafer-scale architectures have proven essential. These methodologies incorporate yield considerations into the initial design phase, implementing graceful degradation strategies and fault-tolerant interconnect schemes that maintain functionality even with moderate defect levels.
Economic modeling indicates that achieving commercially viable yields requires defect densities below specific thresholds while maintaining acceptable performance levels. Current industry efforts focus on reaching yield rates that make wafer-scale engines cost-competitive with traditional multi-chip solutions, particularly for large-scale AI training applications where the performance benefits justify the manufacturing complexity.
The fundamental challenge stems from the statistical nature of semiconductor defects across large silicon areas. Traditional chip manufacturing achieves acceptable yields by producing hundreds of smaller dies per wafer, where individual defective units can be rejected without affecting others. However, wafer-scale engines encompass the entire wafer surface, meaning any critical defect could potentially compromise the entire system's functionality.
Advanced defect tolerance mechanisms have emerged as primary solutions to address yield challenges. These include redundant processing elements distributed across the wafer surface, allowing the system to bypass defective cores while maintaining overall computational capacity. Dynamic reconfiguration capabilities enable real-time mapping around faulty regions, ensuring continued operation despite localized failures.
Process control optimization plays a crucial role in maximizing manufacturing yields. Enhanced lithography techniques, improved chemical mechanical planarization, and advanced metrology systems help reduce defect density across the wafer surface. Statistical process control methods enable manufacturers to identify and correct variations before they impact yield rates significantly.
Innovative design-for-manufacturability approaches specifically tailored for wafer-scale architectures have proven essential. These methodologies incorporate yield considerations into the initial design phase, implementing graceful degradation strategies and fault-tolerant interconnect schemes that maintain functionality even with moderate defect levels.
Economic modeling indicates that achieving commercially viable yields requires defect densities below specific thresholds while maintaining acceptable performance levels. Current industry efforts focus on reaching yield rates that make wafer-scale engines cost-competitive with traditional multi-chip solutions, particularly for large-scale AI training applications where the performance benefits justify the manufacturing complexity.
Thermal Management Solutions for Large-Scale AI Chips
Thermal management represents one of the most critical engineering challenges in wafer-scale AI chip architectures, where traditional cooling methodologies prove inadequate for handling the unprecedented power densities and heat generation patterns. The fundamental challenge stems from the massive scale of these processors, which can contain hundreds of thousands of processing cores distributed across silicon wafers measuring up to 300mm in diameter, generating thermal loads that can exceed several kilowatts per square centimeter in localized hotspots.
Advanced liquid cooling solutions have emerged as the primary approach for addressing these thermal constraints, utilizing direct-to-chip cooling architectures that employ microfluidic channels etched directly into the silicon substrate. These systems typically implement two-phase cooling mechanisms, where specialized coolants undergo phase transitions to maximize heat transfer efficiency. The integration of micro-jet impingement cooling arrays enables targeted thermal management for specific processing clusters, allowing for dynamic thermal control based on computational workload distribution.
Innovative thermal interface materials play a crucial role in optimizing heat transfer pathways between the silicon die and cooling infrastructure. Next-generation thermal interface materials incorporating carbon nanotube arrays and graphene-enhanced compounds achieve thermal conductivities exceeding 2000 W/mK, significantly outperforming traditional thermal pastes. These materials must maintain their properties across wide temperature ranges while accommodating the mechanical stresses inherent in large-scale silicon structures.
Distributed thermal monitoring systems utilize thousands of embedded temperature sensors across the wafer surface, enabling real-time thermal mapping with sub-millimeter spatial resolution. Machine learning algorithms process this thermal data to predict hotspot formation and automatically adjust cooling parameters, preventing thermal runaway conditions that could damage the silicon substrate or degrade processing performance.
Architectural innovations include the implementation of thermal-aware workload scheduling, where computational tasks are dynamically distributed across the wafer based on real-time thermal conditions. This approach maximizes processing throughput while maintaining optimal operating temperatures across all regions of the chip, ensuring consistent performance and extending the operational lifespan of these complex systems.
Advanced liquid cooling solutions have emerged as the primary approach for addressing these thermal constraints, utilizing direct-to-chip cooling architectures that employ microfluidic channels etched directly into the silicon substrate. These systems typically implement two-phase cooling mechanisms, where specialized coolants undergo phase transitions to maximize heat transfer efficiency. The integration of micro-jet impingement cooling arrays enables targeted thermal management for specific processing clusters, allowing for dynamic thermal control based on computational workload distribution.
Innovative thermal interface materials play a crucial role in optimizing heat transfer pathways between the silicon die and cooling infrastructure. Next-generation thermal interface materials incorporating carbon nanotube arrays and graphene-enhanced compounds achieve thermal conductivities exceeding 2000 W/mK, significantly outperforming traditional thermal pastes. These materials must maintain their properties across wide temperature ranges while accommodating the mechanical stresses inherent in large-scale silicon structures.
Distributed thermal monitoring systems utilize thousands of embedded temperature sensors across the wafer surface, enabling real-time thermal mapping with sub-millimeter spatial resolution. Machine learning algorithms process this thermal data to predict hotspot formation and automatically adjust cooling parameters, preventing thermal runaway conditions that could damage the silicon substrate or degrade processing performance.
Architectural innovations include the implementation of thermal-aware workload scheduling, where computational tasks are dynamically distributed across the wafer based on real-time thermal conditions. This approach maximizes processing throughput while maintaining optimal operating temperatures across all regions of the chip, ensuring consistent performance and extending the operational lifespan of these complex systems.
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