A configurable FPGA tile combines integer and floating-point arithmetic with integrated memory and cascade links to boost bandwidth and cut routing delay.
By combining sensing elements with in-memory computing, this case cuts data transfer, latency, wiring complexity, and energy use.
Automatic scenario validators detect unwanted behaviors in autonomous vehicle simulations, filtering noisy data before model training.
One CIM circuit switches between integer and floating-point MAC modes to raise hardware utilization and cut dedicated area overhead.
A monitored partial sum triggers reduced-voltage or skipped memory reads in MAC operations, cutting energy use while preserving accuracy.
An input-stationary MAC circuit reduces RNN weight reloading and input memory accesses by about four times.