Sensing-Memory Computing Cells for Low-Latency In-Situ Signal Processing
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Solution Overview
Problem
Conventional hardware implementations for sensing systems face high energy consumption, low processing speed, and security issues due to large data transfers, which are not suitable for real-time low-power processing in intelligent electronic devices.
Innovation Solution
A sensing-memory-computing synergy (SMCS) device that integrates sensing elements with in-memory computing, using resistive or capacitive sensors to perform operations by controlling voltages on wordlines and bitlines, enabling in-situ sensing, memory, and computing with reduced wiring and control complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional hardware implementation directly senses analog signals and converts to digital signals for post-processing, then measurement precision is improved, but energy consumption increases and processing speed decreases
Solution Approach 1:
The patent merges sensing, memory, and computing functions into a single integrated device. The sensing elements (photodetectors) directly generate electrical signals that are processed through resistive memory cells performing analog multiply-accumulate operations, eliminating the need for separate analog-to-digital conversion and digital processing stages, thereby reducing energy consumption while maintaining processing accuracy
Solution Approach 2:
The patent replaces the conventional mechanical/electronic sequence of analog signal conversion and digital processing with an analog computing system based on resistive memory devices. The physical resistance values in the memory cells directly perform multiplication operations through Ohm's law, substituting complex digital computation with simpler physical laws, reducing energy consumption and processing time
2Measurement precision
If conventional hardware implementation directly senses analog signals and converts to digital signals for post-processing, then measurement precision is improved, but processing speed decreases
Solution Approach 1:
The patent merges sensing, memory, and computing functions into a single integrated device. The sensing elements (photodetectors) directly generate electrical signals that are processed through resistive memory cells performing analog multiply-accumulate operations, eliminating the need for separate analog-to-digital conversion and digital processing stages, thereby reducing energy consumption while maintaining processing accuracy
Solution Approach 2:
The patent replaces the conventional mechanical/electronic sequence of analog signal conversion and digital processing with an analog computing system based on resistive memory devices. The physical resistance values in the memory cells directly perform multiplication operations through Ohm's law, substituting complex digital computation with simpler physical laws, reducing energy consumption and processing time
3Measurement precision
If conventional hardware implementation directly senses analog signals and converts to digital signals for post-processing, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges sensing, memory, and computing functions into a single integrated device. The sensing elements (photodetectors) directly generate electrical signals that are processed through resistive memory cells performing analog multiply-accumulate operations, eliminating the need for separate analog-to-digital conversion and digital processing stages, thereby reducing energy consumption while maintaining processing accuracy
Solution Approach 2:
The resistive memory cells serve multiple functions: they act as both memory storage elements and computing elements. The same physical device performs both data storage (through resistance states) and data processing (through analog multiply-accumulate operations), eliminating the need for separate memory and processing circuits, thereby reducing wiring and control complexity
4Reliability
If NVM-based IMC is used to store weights during power-off, then reliability is improved, but energy consumption increases due to high write operation energy
Solution Approach 1:
The patent uses eDRAM with selectively activated storage capacitors. Only the storage capacitors corresponding to currently needed weight values are activated and maintained, while others are in a low-power state. This partial activation reduces overall energy consumption compared to maintaining all NVM weights in a high-reliability state, while still providing sufficient reliability for the active computing weights
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SMCS device lowers computing latency and improves energy efficiency and robustness by integrating sensing and computing functions, reducing data transmission overhead and enhancing reliability in complex environments.
Implementation Method 1
the sensing elements include resistive sensors or capacitive sensors, and the stored value of the SMCS device is represented by at least one of the total initial resistance of the resistive sensor under a first preset input condition
Implementation Method 2
the sensing elements include resistive sensors or capacitive sensors, and the stored value of the SMCS device is represented by at least one of the total initial capacitance of the capacitive sensor under a second preset input condition
Implementation Method 3
a control module connected to the wordlines and bitlines of each SMCS cell, wherein the control module is configured to control the voltages of each wordline and bitline so that the SMCS cell can perform desired operations
Data Source
AI summary
The present disclosure relates to a sensing-memory-computing synergy device, chip and electronic device. The said device comprises: at least one sensing-memory-computing synergy cell, wherein each sensing-memory-computing synergy cell comprises K sensing elements, where the first end of each sensing element is connected to wordline, the second end of each sensing element is connected to bitline, the sensing element can sense changes in external inputs, and K is an integer greater than or equal to zero; a control module which controls the voltages of each wordline and bitline so that the sensing-memory-computing synergy cell can perform desired operations, and sense the voltage or current on bitlines to obtain the operation results. The present embodiment of the disclosure implements the sensing-memory-computing synergy cell by sensing elements, which combines sensing and in-memory computing. The sensing elements gather sensor data from external inputs, and the sensing-memory-computing synergy operation is performed by controlling the voltages on wordlines and bitlines. The present embodiment of the disclosure enables the in-situ sensing, memory and computing functions in a device with decreased wiring and control complexity, which lowers the computing latency and improves robustness and energy efficiency.