Computations Using Pulse Rate Multipliers/Dividers TRIZ Cases
- Recirculating Delay Frequency Doubler for 50% Duty Cycle Clocks
A recirculating delay circuit and divide-by-two loop doubles two-phase clocks while maintaining 50% duty cycle and reducing buffer count.
- Balanced Frequency Quadrupler Using Quadrature-Coupled Doublers
A hybrid coupler drives balanced doublers in quadrature to cancel reflected power and improve 160 GHz frequency multiplication efficiency.