Recirculating Delay Frequency Doubler for 50% Duty Cycle Clocks
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Solution Overview
Problem
Existing frequency doubler circuits lack efficiency in power management and precise duty cycle control, particularly in generating a 50% duty cycle output for multi-phase clock systems.
Innovation Solution
The frequency doubler circuit incorporates a multiplexer, a recirculating delay circuit with a logic gate and cascaded clock buffers, and a divide-by-two circuit to efficiently double the frequency of a two-phase clock with a 50% duty cycle, utilizing a power supply node to adjust delays for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a digitally controlled delay circuit is used for duty cycle control, then the frequency doubling function is achieved, but power efficiency deteriorates
Solution Approach 1:
The patent extracts the essential delay function from a complex digitally controlled delay circuit and implements it using a minimal structure: a single D-flip-flop combined with a simple delay element. This extraction removes unnecessary digital control logic and reduces power consumption while maintaining the frequency doubling capability.
Solution Approach 2:
The D-flip-flop automatically performs the duty cycle correction function by capturing the phase information from the input clock and generating the appropriate control signals for the multiplexer. The circuit self-regulates the duty cycle without requiring external digital control, thereby reducing overall power consumption.
2Measurement precision
If multiple clock buffers are used in the delay chain, then the delay precision is improved, but device complexity increases
Solution Approach 1:
Instead of using multiple clock buffers to achieve precise delay, the patent employs a single delay element with carefully selected characteristics that provide sufficient delay precision for the application. This partial action approach achieves the required precision without the excessive complexity of multiple buffers.
Solution Approach 2:
The patent changes the approach from increasing quantity (multiple buffers) to optimizing quality (single buffer with optimized delay parameter). By adjusting the delay element's characteristics such as propagation delay or physical dimensions, the circuit achieves the required precision with minimal complexity.
Data Source
AI summary
A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.