Computing Operation Arrangements TRIZ Cases
- SR Latch Time Amplifier Bias Control for Linear Input Range
Dynamic SR latch bias and resistance control broadens time-amplifier input range while keeping gain linear and stable.
- Single-Transistor RF Mixing for LO Leakage and Image Rejection
By mixing PA input and output spectra in one transistor, this case detects LO leakage and image rejection while cutting chip area and power.
- Linearized Mixer Input Stage for Third-Order Distortion Cancellation
A differential-pair linearizer cancels third-order distortion in the mixer input stage, extending dynamic range and improving IIP3.
- Analog Baseband Filter Blocks With Shared Capacitors for Multi-Mode RF
Shared capacitors and switchable filter blocks let wireless transceivers cover 2G to 4G baseband bandwidths with less area and noise.
- Multi-Section Output Signal Circuit for Ramped Gain Control
Multiple circuit sections with adjustable offsets combine partial signals to shape ramped gain curves and improve output control accuracy.
- Double-Spiral Dual-Balanced Mixer Layout for Compact MMW ICs
A double-spiral balun layout shrinks dual-balanced MMW mixer area to about 15% of star-type designs while preserving mixing characteristics.
- 3D Double-Spiral Dual-Balanced Mixer for Compact IC Layouts
A multilayer double-spiral balun layout shrinks dual-balanced mixer area to about 15% of star-type designs while preserving MMW mixing.
- PVT-Compensated Delay Timing for Stable On-Chip Reference Signals
Delay modules compare phase and frequency shifts to detect PVT changes and correct an on-chip oscillator for stable absolute timing.