Concurrent Instruction Execution TRIZ Cases
- Out-of-Order Queue Entry Selection Using Parallel Bit Vectors
Parallel mask, executable, and selection bit vectors simplify out-of-order queue entry selection to cut delay, power, and chip area.
- ALU Slot Packing for Parallel VLIW Instruction Execution
Packing non-conflicting operations into one ALU slot enables parallel VLIW execution, improving hardware utilization and processing efficiency.
- Circular Queue Wrap-Bit Validation for Speculative Reads
Wrap-bit validity checks enable nondestructive speculative reads in a circular queue, improving processor performance without extra gates.
- Next PC Cache Branch Prediction Using Local History Registers
Local history in a direct next PC cache improves branch target prediction and cuts pipeline stalls in deeply pipelined processor cores.
- Token-Based Integrated-Circuit Architecture for Low-Latency Edge AI
Token-based governance coordinates data flow across local processing tiles, reducing latency and energy use for real-time edge AI inference.