Out-of-Order Queue Entry Selection Using Parallel Bit Vectors
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Solution Overview
Problem
The selection logic for choosing executable entries from an out-of-order processor queue is complex, leading to delays, increased power consumption, and a larger chip area, which affects processor performance.
Innovation Solution
A method and apparatus that generate mask, executable, and selection bit vectors based on tag values and indication information to determine executable entries, allowing parallel selection and reducing selection complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex selection logic is used to select executable entries from the queue, then the selection accuracy is improved, but the selection delay increases and processor performance decreases
Solution Approach 1:
The selection logic is segmented into multiple independent modules: a mask bit vector generation module that creates selection masks based on queue entry states, and a selection module that uses these masks to efficiently identify executable entries. This segmentation allows parallel processing of selection criteria without increasing overall delay.
Solution Approach 2:
The patent changes the parameter representation from complex conditional logic to simplified bit vector parameters. By representing queue entry states as bit vectors and using bitwise operations, the selection process achieves high accuracy with reduced computational delay.
2Measurement precision
If complex selection logic is used to select executable entries from the queue, then the selection accuracy is improved, but the power consumption increases
Solution Approach 1:
The selection logic is divided into independent modular components that can be selectively activated. The mask bit vector generation module processes only relevant queue entries based on current execution state, reducing unnecessary power consumption while maintaining selection accuracy.
Solution Approach 2:
Complex mechanical-style conditional logic is replaced with efficient bitwise operations and boolean algebra. This substitution reduces the computational complexity and power consumption of the selection process while preserving accurate identification of executable entries.
3Measurement precision
If complex selection logic is used to select executable entries from the queue, then the selection accuracy is improved, but the chip area increases
Solution Approach 1:
Multiple selection criteria and state checks are merged into unified mask bit vectors. By combining multiple selection conditions into single bitwise operations, the patent reduces the number of separate logic circuits needed, thereby reducing chip area while maintaining comprehensive selection accuracy.
Solution Approach 2:
The mask bit vector generation module serves multiple functions: it tracks queue entry validity, execution readiness, and priority status simultaneously. This multi-functionality eliminates the need for separate dedicated circuits for each selection criterion, reducing overall chip area.
Data Source
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AI summary
Provided are a method and an apparatus for selecting an entry of a queue in an out-of-order processor, an electronic device, a storage medium, a computer program product, and a computer program. The method includes: generating a mask bit vector of the queue based on the tag value of each entry; generating an executable bit vector of the queue based on whether the entry in the queue satisfies an executable condition; generating a selection bit vector of the queue based on the mask bit vector and the executable bit vector; and determining an entry corresponding to a target bit in the selection bit vector as an executable entry, in which the target bit is a first bit in the selection bit vector with a corresponding value being a first preset value.