Concurrent Instruction Execution TRIZ Cases
- Register Index Segmentation for Out-of-Order Wake-Up Logic
Segmenting register indices into common and unique bits reduces comparator count and power consumption while maintaining wake-up logic accuracy.
- Fuse Input Instructions for JPEG Data Block Processing
A fuse input instruction selects and sign extends portions of two input vectors to shuffle data elements into output vectors.
- Streaming Multiprocessor Uniformity Detection for Power Reduction
A streaming multiprocessor detects uniform operand sets to consolidate execution into a single anchor thread operation.
- Constant Cache Forwarding Literal Values to Eliminate Pipeline Stalls
A constant cache stores literal values during decode for immediate operand forwarding, eliminating pipeline stalls caused by data dependency delays.
- Qualified Branch Instruction Mechanism for Memory Reconfiguration Hazards
A qualified branch instruction mechanism overrides prediction to enforce execution order after memory area selection changes.
- Move Elimination Circuitry for Processor Pipeline Optimization
Demotion circuitry reverses move elimination adjustments when Rename Commit Queue capacity limits are reached, preventing pipeline stalls.
- Thread Pause Processor Back-End Resource Management
A thread pause instruction empties processor back-end execution units to free resources for other threads.
- Composite Scalar-Vector VLIW Instruction Execution Unit
A composite VLIW instruction execution unit combines scalar and vector operations within a single instruction cycle.
- Multi-Slice Processor Dynamic Partial Load Cancellation
Dynamic canceling of partial loads in multi-slice processors reduces execution cycles and power consumption by preventing issuance of incomplete operations.