Fuse Input Instructions for JPEG Data Block Processing
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Solution Overview
Problem
Processor architectures with SIMD instructions do not effectively improve throughput when decoding data objects encoded using techniques like entropy encoding, as decoding is mostly a serialized process due to variable length codes, making it difficult to split input data for parallel processing.
Innovation Solution
A hardware decoder is integrated with the processor to accelerate decoding, utilizing pipelined operations and machine instructions to handle parallelizable steps with SIMD instructions and serial steps separately, allowing for efficient processing of compressed data objects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If SIMD instructions are used to accelerate decoding, then computational parallelism is improved, but decoding throughput does not improve because entropy encoding creates serialized processing requirements
Solution Approach 1:
The patent segments the decoding process into distinct phases: variable-length code decoding (performed by hardware decoder), inverse transform (performed by SIMD processor), and other post-processing operations. This segmentation allows each component to operate in its optimal mode - the hardware decoder handles the serialized nature of entropy decoding while the SIMD processor handles parallelizable operations, resolving the contradiction between parallelism capability and throughput performance.
Solution Approach 2:
The patent introduces a specialized hardware decoder as an intermediary component between the compressed data input and the SIMD processor. This intermediary handles the variable-length code decoding that inherently requires sequential processing, then passes fixed-width output to the SIMD processor for parallel processing of subsequent operations. The intermediary resolves the conflict by isolating the serialized portion from the parallel processing pipeline.
2Loss of time
If hardware decoder is integrated with processor, then decoding latency is reduced, but device complexity increases
Solution Approach 1:
The patent merges the hardware decoder and SIMD processor into a single integrated decoding system with shared memory and coordinated control. This merging allows the two components to work closely together with efficient data transfer, minimizing latency while avoiding the complexity of completely separate systems. The integrated architecture shares resources and coordination logic, reducing overall system complexity compared to fully independent components.
Data Source
AI summary
Techniques to take advantage of the single-instruction-multiple-data (SIMD) capabilities of a processor to process data blocks can include implementing an instruction to fuse the data blocks together. The fuse input instruction can have a first input vector, a second input vector, a select input, a first output vector, and a second output vector. The fuse input instruction selects a portion of the first input vector and a portion of the second input vector based on the select input, sign extends the selected portion of the first input vector and the selected portion of the second input vector, and shuffles data elements of the sign extended portion of the first input vector with data elements of the sign extended portion of the second input vector to generate the first and second output vectors.