Electronic Circuit Testing TRIZ Cases
- TSV Transfer Chain Circuit for Layer-by-Layer 3D IC Testing
A serial TSV transfer chain enables layer-by-layer 3D IC connectivity testing while reducing the extra test TSVs that consume chip area.
- Metal Gate Self-Heating for In-Line Semiconductor Reliability Testing
Using the metal gate as a local heater speeds semiconductor reliability testing to 200°C-400°C while avoiding wafer transfer damage.
- Battery Pack Capacitor Defect Detection Using Noise Signals
Noise-signal impedance measurement detects defective battery-pack filter capacitors without disassembly, improving voltage accuracy and pack reliability.
- Backside Substrate Openings for Buried Metal Layer Testing
Backside substrate openings expose buried metal layers for semiconductor analysis while avoiding front-side damage and complex cut-and-repair steps.
- Wafer Fracture Analysis Workflow With FOUP Identifier Tracking
Automated FOUP transfer and wafer-piece ID linking improve wafer fracture analysis reliability, positioning accuracy, and safety.