TSV Transfer Chain Circuit for Layer-by-Layer 3D IC Testing
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Solution Overview
Problem
In 3D integrated circuits (ICs), the numerous test through silicon vias (TSVs) required for testing connectivity reduce the effective utilization rate of the chip due to the need for multiple TSVs to transfer test signals, leading to a low effective area and utilization.
Innovation Solution
A signal transmission circuit with a serially-connected transfer chain of stages, where each stage is connected via a TSV, and an input circuit generates a test signal that is transferred stage by stage, allowing for efficient layer-by-layer testing of TSV connectivity without the need for extensive TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test TSVs are provided for testing connectivity in 3D ICs, then the reliability of TSV connectivity testing is improved, but the effective utilization rate of the chip is reduced
Solution Approach 1:
The patent combines multiple test signal transmission functions into a single TSV by using a serial transfer chain architecture. Instead of dedicating separate TSVs for each test signal, the invention merges the functionality of multiple test TSVs into one by sequentially transferring test signals through multiple stages within a single TSV, thereby reducing the total number of TSVs required and improving chip effective utilization rate while maintaining testing reliability
Solution Approach 2:
The patent segments the test signal transmission process into multiple stages within a serial transfer chain. The test signal is divided into multiple segments that are transferred sequentially through different stages in the transfer chain, allowing a single TSV to perform the function of multiple TSVs would have been needed, thus resolving the contradiction between testing reliability and chip utilization
2Measurement precision
If multiple test TSVs are used for layer-by-layer testing, then the measurement precision of TSV connectivity is improved, but the device complexity increases
Solution Approach 1:
The patent implements a universal transfer chain structure where a single multi-functional circuit can test multiple TSVs and multiple chip layers. The transfer chain is designed to be reconfigurable and can sequentially test different TSV connections and different layers, eliminating the need for dedicated test circuits for each TSV or layer, thus reducing device complexity while maintaining measurement precision
Solution Approach 2:
The patent employs dynamic control of the transfer chain to adaptively route test signals to different destinations based on testing requirements. The serial transfer chain can dynamically reconfigure its operation mode to test different TSV connections or different chip layers, providing a flexible, low-complexity solution that maintains high measurement precision through programmable control
Data Source
AI summary
A signal transmission circuit and method for testing an integrated circuit (IC) are disclosed. The signal transmission circuit includes: an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal; a transfer chain, including multiple stages of serially-connected transfer circuits, where adjacent transfer circuits in the transfer chain are connected via a through silicon via (TSV), the transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal in stage by stage in response to the clock signal; and multiple signal output ends, where a first test signal input end of each stage of transfer circuit is correspondingly connected to one signal output end. The signal transmission circuit improves the effective utilization rate of a chip in an IC having a TSV test circuit.