Variable finger pitch in a CMOS FinFET resonator enables tunable clock frequency while reducing chip area and power use.
A π-type output-side switching layout cuts resistor and switch count to save area, lower parasitic capacitance, and preserve impedance matching.
Integrated coil, capacitor, and inverter paths bring wideband DSA onto the IC while preserving receiver linearity and ADC dynamic range.
Variable FET on-resistance enables precise RF attenuator gain trimming without tiny resistors, preserving signal waveform and return loss.
Parallel transistor switches vary attenuation with signal amplitude to prevent clipping and saturation while preserving linearity.
A dual-mode VVA combines DAC programming with external analog control to smooth RF attenuation changes and reduce modulation errors.
Combining a programmable VVA with a DSA enables smooth RF attenuation changes, improving signal accuracy and calibration range.
Parallel NFET and PFET shunt arms use complementary gate control to cancel RF nonlinearity and improve IP3, IM3, and attenuation consistency.
Selectable continuous attenuation ranges use DAC and FET control to avoid abrupt RF level changes while preserving precise signal linearity.
Parallel NFET and PFET shunt arms use complementary gate bias to cancel RF nonlinearity and improve VVA IP3 and IM3.
A hybrid thermometer-binary attenuator cuts switching glitches by limiting simultaneous stage transitions while preserving fast step changes.
Body-voltage control keeps MOS drain-source resistance linear across a voltage range, helping signal-conditioning circuits handle variation and temperature.