Instruction Analysis TRIZ Cases
- Memristor-Based RISC Processor for Von Neumann Bottleneck
A memristor-based reduced instruction set processor fuses computation and memory to eliminate data movement overhead.
- Arithmetic Operation With Shift Instruction
A single arithmetic operation with shift instruction trims intermediate results to desired precision, reducing latency and power consumption.
- Secure Instruction Pipeline for Out-of-Order Execution
Segmenting the execution path into secure and non-secure pipelines resolves the contradiction between high throughput and instruction integrity.
- Programmable Logic Processor Configuration via DSP and Memory Blocks
Combining DSP blocks with embedded memory forms processors, reducing general-purpose logic consumption.
- Scatter Gather Index Array Finite State Machine
Index array and finite state machine generate addresses for scatter gather operations, reducing clock cycles from noncontiguous memory access.