Programmable Logic Processor Configuration via DSP and Memory Blocks
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Solution Overview
Problem
Existing programmable logic devices (PLDs) face challenges in efficiently utilizing resources when implementing processors, as both soft processor configurations consume significant general-purpose logic resources and dedicated processors occupy valuable area without being fully utilized.
Innovation Solution
Incorporating embedded memory blocks and DSP blocks with an instruction sequencing unit and dedicated instruction bus, allowing these blocks to function together as processors, thereby minimizing resource consumption and enabling user-defined interconnections for efficient processor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a soft processor configuration is used, then processor functionality is achieved, but general-purpose logic resources are significantly consumed
Solution Approach 1:
The patent combines specialized processing blocks (DSP blocks with multipliers, adders, registers) and embedded memory blocks into an integrated processor unit. This merging allows the processor to achieve full functionality while consuming fewer total resources than a soft processor would require, as the specialized blocks handle specific operations efficiently rather than relying entirely on general-purpose logic.
Solution Approach 2:
The processor configuration uses programmable interconnect resources and configurable processing elements that can perform multiple functions. The same DSP blocks and memory structures serve both as specialized processing units and as general-purpose resources when not engaged in processor operations, increasing overall resource utilization efficiency.
2Quantity of substance
If a dedicated processor is provided, then processor functionality is achieved with minimal resource consumption, but device area is occupied that could be used for general-purpose logic
Solution Approach 1:
The processor configuration is dynamic and reconfigurable rather than fixed. Users can programmatically configure which processing blocks and memory elements form the processor, and these configurations can be changed via instruction sequences. This dynamic approach allows the same hardware structures to adapt between processor mode and general-purpose logic mode, eliminating the need for permanently dedicated processor circuitry.
Solution Approach 2:
The device is segmented into multiple independent processing blocks and memory blocks that can be selectively combined to form a processor. This segmentation allows fine-grained control over resource allocation, enabling the processor to use only the specific blocks needed for a given application while leaving other blocks available for general-purpose logic functions.
3Adaptability or versatility
If a fixed number of dedicated processors are provided, then processor functionality is available, but users needing more processors cannot implement additional ones
Solution Approach 1:
Rather than providing a fixed number of complete processors, the patent provides a set of processing blocks and memory blocks that can be partially combined to form one or more processors depending on user needs. Users can configure the blocks to create a single large processor or multiple smaller processors, allowing flexible scaling without requiring pre-defined processor counts.
Data Source
AI summary
A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of embedded memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Instruction sequencing circuitry is provided, and the instruction sequencing circuitry, at least one of the specialized processing blocks and at least one of the embedded memory modules, are programmably connectable to form a processor, where the memory module serves as instruction memory. Optionally, a dedicated instruction bus communicates the instructions from the embedded memory module or modules to the specialized processing block or blocks.