Memory Architecture Accessing/Allocation TRIZ Cases
- Flash Memory Data Management Compressible Data Segmentation
Segmenting physical programming units stores compressed data and management information in separate areas, preserving error checking capability.
- Shared Ring Buffer Cache-Line Bounce Reduction
Offset storage separates producer and consumer cache lines in a shared ring buffer, eliminating bounce bottlenecks that degrade throughput.
- Content-Based Cache Failover for Virtual Hosts
A fail-over cache populates by copying or merging content-based read caches from host systems.
- Repeat Cache for Multi-Thread Code Reuse
A repeat cache stores code segments for shared access across concurrent threads in a barrel-threaded processor.
- Memory Controller Buffer Data Protection During Long Procedures
A memory control circuit unit temporarily stops receiving write data during long execution procedures to prevent buffer loss.