Shared Ring Buffer Cache-Line Bounce Reduction
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Solution Overview
Problem
Shared memory ring configurations experience performance bottlenecks due to cache-line bounces, particularly in light-use scenarios where the ring is mostly empty, leading to significant slowdowns and reduced throughput.
Innovation Solution
Implementing a shared ring buffer with a partially overlapping active and processed ring buffer configuration, where requests are stored at specific offsets to create a spacing between the producer and consumer processors, preventing cache-line bounces by ensuring they access different cache-lines, and extending the shared memory area to accommodate a maximum number of outstanding requests without doubling the ring size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a shared memory ring configuration is used, then memory utilization is improved, but cache-line bounces occur causing performance degradation
Solution Approach 1:
The ring buffer is segmented into multiple cache-lines, with the producer and consumer accessing different cache-lines. The ring buffer structure is divided such that the producer writes to one cache-line while the consumer reads from another, preventing cache-line bouncing between processors while maintaining shared memory access.
2Productivity
If the ring buffer size is increased to accommodate more requests, then throughput is improved, but memory usage increases
Solution Approach 1:
The patent introduces a dimensional separation by using different cache-lines for producer and consumer accesses. Instead of increasing the ring buffer size linearly, the solution exploits the cache-line dimension to allow parallel access patterns, effectively increasing throughput without proportional memory increases.
3Ease of operation
If the producer and consumer access adjacent slots in the ring buffer, then memory access pattern is simplified, but cache-line bounces increase
Solution Approach 1:
The patent introduces asymmetry in the memory access pattern by offsetting the producer and consumer access points to different cache-lines. Instead of symmetric adjacent slot access, the producer and consumer access asymmetrically positioned slots that fall into different cache-line boundaries, preventing bounce while maintaining operational simplicity.
Data Source
AI summary
A system includes a memory, a producer processor and a consumer processor. The memory includes a shared ring buffer, which has a partially overlapping active ring and processed ring. The producer processor is in communication with the memory and is configured to receive a request associated with a memory entry, store the request in a first slot of the shared ring buffer at a first offset, receive another request associated with another memory entry, and store the other request in a second slot (in the overlapping region adjacent to the first slot) of the shared ring buffer. The consumer processor is in communication with the memory and is configured to process the request and write the processed request in a third slot (outside of the overlapping region at a second offset and in a different cache-line than the second slot) of the shared ring buffer.