Physical Realisation TRIZ Cases
- Processor Accelerator Memory Mode Switching for Cache Management
Dynamic mode switching in processor accelerator memory manages cache eviction paths.
- Augmented Recurrent Neural Network External Memory
External memory integration resolves bounded capacity limits by enabling continuously differentiable stack, queue, and double-ended queue implementations.
- Matrix Index Bit String Generation for Sparse Data
A bit string generator creates constant-sized matrix index information by encoding element positions within a unified data structure.
- Neural Network Arithmetic Device Activation Function Look-Up Table
Arithmetic device stores activation functions in look-up tables for rapid retrieval during neural network inference.
- Neural Network Filter Compression via Layer-Wise Normalization
A neural network compression method normalizes filter importance scores layer by layer to selectively remove redundant filters.
- Client-Server Neural Network Processing via Byte Array Transmission
A client transmits atomic data as byte arrays to a server for neural network processing without format conversion.
- In Situ Backpropagation for Photonic Neural Network Training
Calculating loss and computing adjoint inputs enables in situ backpropagation, eliminating external simulations that hinder training efficiency.
- ktRAM Neuromorphic Memory Using AHaH Nodes and Memristors
A ktRAM architecture merges memory and processing using AHaH nodes and memristive components for simultaneous data readout.
- Convolution Computing Apparatus Parallel Processing Optimization
A computing apparatus divides input feature maps and weights into blocks for parallel processing by master and slave circuits.
- All-Photonic Neural Network Processor Via Nonlinear Optics
A photonic neural network processor encodes information in ring resonator frequency modes.
- Bank-Balanced Sparsity for Neural Network Compression
Segments weight matrices into equal-sized banks pruned uniformly to balance model accuracy with hardware speedup.
- Neural Network Quantization With Adaptive Scale Parameters
A shifter and decoder configuration uses scale parameters to minimize quantization error in neural network accelerators.
- Magnetic Domain Synapse Circuit for Neural Network Weight Tuning
Non-volatile magnetic memory arrays store and tune synaptic weights directly within the input circuit.
- Compiler Buffer Allocation for Neural Network Tensor Operations
A compiler allocates buffer space for binary tensor operations based on operand instance counts.
- Switchable Sparsity Acceleration in DNN Load Modules
A load module configures deep neural network accelerators to dynamically select between weight and activation sparsity modes for efficient processing.
- Budding Ensemble Neural Network Diversity Loss Training
A budding ensemble neural network uses diversity loss to train multiple heads with different internal parameters for improved object detection.
- In-Memory Compute Structure for Convolutional Neural Network Energy Reduction
A cache and compute structure rotates loaded data to enable in-memory arithmetic operations without external memory access.
- Continual Refinable Network for Edge Device Learning
A continual refinable network directs gradients to flat local minima using a dynamic learning rate.