Processor Accelerator Memory Mode Switching for Cache Management
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Solution Overview
Problem
Current processors face challenges in efficiently handling neural network computations due to limitations in cache management and data processing, which affect performance and efficiency in deep learning applications.
Innovation Solution
A processor architecture with a neural network unit (NNU) that includes a processing core, a data storage system with a tag directory and mode indicator, and control logic to manage cache lines and accelerator data, allowing for dynamic operation modes to optimize cache eviction and memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the accelerator data storage is used as victim cache to store evicted cache lines, then cache management efficiency is improved, but the accelerator cannot process data stored in this memory
Solution Approach 1:
The accelerator data storage is configured to dynamically switch between two operational modes: victim cache mode for storing evicted cache lines and accelerator data storage mode for holding accelerator data. This dynamic reconfiguration allows the same memory resource to serve different functions based on operational needs, resolving the contradiction between cache management efficiency and accelerator data processing capability.
Solution Approach 2:
The accelerator data storage is designed with multi-functionality, serving both as a victim cache for cache management and as a storage for accelerator data processing. By implementing mode switching between victim cache mode and accelerator data storage mode, the system achieves universal usage of the memory resource, eliminating the need for separate dedicated storage structures.
2Adaptability or versatility
If the processor architecture includes dynamic mode switching between victim cache and accelerator data storage, then adaptability is improved, but device complexity increases
Solution Approach 1:
A single accelerator data storage structure is designed to perform multiple functions through mode switching, eliminating the need for separate dedicated victim cache and accelerator data storage structures. This multi-functional design achieves operational mode flexibility while minimizing the addition of separate hardware components.
Solution Approach 2:
The victim cache functionality and accelerator data storage functionality are merged into a single memory structure that can be dynamically reconfigured. This consolidation reduces the overall device complexity by combining what could have been separate memory subsystems into one unified resource with flexible operational modes.
Data Source
AI summary
A first data storage holds cache lines, an accelerator has a second data storage that selectively holds accelerator data and cache lines evicted from the first data storage, a tag directory holds tags for cache lines stored in the first and second data storages, and a mode indicator indicates whether the second data storage is operating in a first or second mode in which it respectively holds cache lines evicted from the first data storage or accelerator data. In response to a request to evict a cache line from the first data storage, in the first mode the control logic writes the cache line to the second data storage and updates a tag in the tag directory to indicate the cache line is present in the second data storage, and in the second mode the control logic instead writes the cache line to a system memory.