Pulse Generation By Super Conductive Devices TRIZ Cases
- Balanced SQUID Coupler Layout for Cross-Talk Cancellation
Two inductively coupled SQUIDs cancel control-current cross-talk while tuning input-to-signal coupling without complex calibration.
- Josephson Flux-Shuttle Current Source for Low-Dissipation Biasing
An AC-driven flux-shuttle loop replaces bias resistors to generate DC current with automatic cutoff, reducing heat and static power in superconducting circuits.
- RQL Phase-Mode Flip-Flop for Persistent SFQ State Capture
Phase-encoded SFQ data is held in a Josephson-junction storage loop and clocked through a comparator to preserve state across AC cycles.
- Superconducting Flux Reset Control for Josephson Junction Asymmetry
Discrete power levels and grouped addressing pulses reset superconducting flux DACs despite junction asymmetry while limiting thermal load.
- Superconducting SFQ Data Alignment Across Opposite-Phase Clocks
Opposite-phase clock windows convert RTZ input pulses into aligned SFQ output pulses for reliable superconducting data transfer across timing domains.
- Superconductor-Semiconductor Readout Circuit for Current-to-Charge Conversion
A nanocryotron-triggered transistor circuit converts stored supercurrent into capacitor charge for low-noise superconducting readout.
- Resonant Clock Rib Topology for Low-Power Superconducting Biasing
AC resonant clock ribs use capacitive and inductive interconnects to bias superconducting circuits with lower power loss and less clocking area.
- SFQ Pulse Multiplier Circuit for RSFQ-CMOS Voltage Interfacing
By splitting, delaying, latching, and recombining SFQ pulses, this circuit multiplies frequency and voltage to ease RSFQ-CMOS interfacing.
- Josephson Transmission Line Clocking for Unipolar SFQ Reset
Quadrature-phase clock transformers let JTL stages self-reset without negative SFQ pulses, simplifying unipolar SFQ transmission.
- Superconducting Circuit Timing with Virtual Retime and Anchor Cells
Virtual anchor and retime cells simplify Josephson-junction timing paths by controlling latency and synchronization for accurate superconducting circuit design.
- Superconducting Rising-Edge Detection With Return-to-Zero Pulses
Josephson-junction stages suppress negative pulses and convert each input rising edge into a low-power return-to-zero signal.
- Josephson Waveform Synthesizer for Jitter-Resistant RF Accuracy
Quantized Josephson pulses and bipolar combining reduce timing jitter sensitivity, enabling accurate high-frequency RF waveform synthesis.
- Josephson RQL Phase-Mode Flip-Flop Without Setup-Hold Reset
SFQ data stored in a Josephson loop is captured by reciprocal clock pulses, enabling reset-free binary storage with low power.
- Isochronous SFQ-to-RQL Receiver for Clock Phase Alignment
An SFQ receiver and converter align RQL data to the AC clock sampling phase, enabling reliable inter-chip transfer despite unknown clock phase.
- Clockless DC-Powered DSFQ Logic With Self-Resetting State
A dynamic storage element with nonlinear flux leakage lets DC-powered DSFQ logic self-reset without a clock and tolerate larger input skew.