An impedance loop and resistor network matches Gigabit Ethernet chips to coaxial cable, enabling reliable high-speed signal transmission.
A same-substrate transducer and capacitor form a compact Bias-Tee that improves RF biasing while reducing parasitics and fabrication complexity.
Common-mode sensing lets one auxiliary driver support voltage- and current-mode pre-emphasis while improving signal and power integrity.
A high-pass impedance transformation keeps the port matched during power-state switching, reducing crosstalk and stabilizing G.fast transmission.
Matched RC-controlled MOSFET switching balances CAN high and low line transitions to cut EMF radiation without large area penalties.
Capacitor coupling cancels transmit signals while a feedback PGA amplifies receive signals, reducing loss and noise at shared ports.
Power-domain NOMA embeds bandwidth requests in DOCSIS data payloads at different power levels, avoiding contention windows and reducing collisions.
A second receiver filters leaked transmitter noise and adds an inverted signal to protect DSL downlink performance.
A dielectric waveguide coupler transmits guided electromagnetic waves along a wire surface without direct electrical contact.
A multi-use optical power interface merges data and energy paths into one connector.
A single networking chipset merges wireless and wired transmission paths to enable concurrent data flow across multiple communication interfaces.
A guided wave switch aligns dielectric cores to couple electromagnetic waves between transmission media.
A differential transformer-free hybrid circuit uses balanced network elements to interface with telephone loops.
A signal transceiving circuit uses a resistance circuit to cancel output noise at the receiver.
Scaling IFFT size and sampling rate reduces resource consumption while maintaining DOCSIS 3.1 compliance.
A passive echo cancellation circuit uses an offset signal to remove transmit interference from full-duplex receive lines.