0T1R Resistive Memory Array for Low-Voltage Write Operation

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Solution Overview

Problem

Conventional Resistive Random Access Memory (RRAM) devices require high write voltages due to large current and IR drop, leading to increased power consumption, area overhead, and difficulty in shrinking logic, primarily because of the need for charge pumps and high voltage devices.

Innovation Solution

The implementation of a zero-transistor and one-resistor (0T1R) RRAM array by bypassing or removing the selector device, eliminating IR drop and reducing the minimum voltage for write operations, and utilizing regulated write voltage circuits, current limiters, and termination circuits to stabilize write operations at lower voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a charge pump and high voltage devices are used in conventional RRAM, then high write voltage is achieved, but power consumption increases and area overhead increases

Engineering Contradiction:
Improvewrite voltageVSAvoidpower consumption
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The patent removes the charge pump and high voltage devices from the RRAM architecture, extracting the voltage boosting function and replacing it with a direct low-voltage write path that achieves sufficient write voltage without additional power-consuming components

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the voltage parameter from high voltage operation to low voltage operation by modifying the write path architecture, enabling the RRAM cell to be programmed effectively at lower voltages through optimized current flow paths

Inventive Principle:
Principle #35Parameter changes

2Power

If a charge pump and high voltage devices are used in conventional RRAM, then high write voltage is achieved, but device area increases

Engineering Contradiction:
Improvewrite voltageVSAvoidarea overhead
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the charge pump and high voltage devices from the RRAM array architecture, eliminating the area overhead associated with these components while maintaining write capability through a simplified low-voltage path

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If selector devices are included in RRAM cells, then cell functionality is maintained, but IR drop increases and write voltage requirement increases

Engineering Contradiction:
Improvecell functionalityVSAvoidwrite voltage
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent removes the selector device from the RRAM cell structure, extracting the source of IR drop and voltage loss, and replaces it with a direct conductive path that eliminates the voltage drop issue while maintaining the ability to selectively program individual cells

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the write path into dedicated low-voltage write lines that bypass the selector device, creating a separate current flow path for write operations that avoids the IR drop problem while maintaining cell selectivity through other means

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption, area overhead, and enables efficient low voltage operations, allowing for faster and more compact RRAM devices suitable for applications like electronic fuses.

Implementation Method 1

Resistive Random Access Memory (RRAM) is a memory technology that uses a change in resistance rather than charge to store bits of information. The resistive switching in RRAM is carried out by SET and RESET operations.

Methodology Applied
Scientific EffectResistive switching: Electrical Resistance

Implementation Method 2

Each memory cell includes an access transistor and an RRAM resistive element. The access transistor has a source terminal, a drain terminal, and a gate terminal. The RRAM resistive element has a first terminal connected to the drain terminal of the access transistor and a second terminal connected to a bit line.

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250292831A1Resistive memory with low voltage operation
Publication Date: 2025.09.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250292831A1 patent drawing
  • US20250292831A1 patent drawing
  • US20250292831A1 patent drawing

AI summary

A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.