Digital Storage TRIZ Cases

A single global switch with local bit-line and word-line switches reduces peripheral area while supplying memory cells.

A multiplexing circuit switches CA signal handling between high-speed operation and low-speed testing, allowing standard equipment to test semiconductor memory.

An inclined underlayer lets MTJ elements use varied insulating-layer thicknesses in one deposition, reducing etch blockage and redeposit defects.

Small FTJ resistance-state changes limit read accuracy and speed; a higher-capacitance second capacitor amplifies the current difference.

A memory control unit detects identical strobe logic states and generates complementary outputs to support JEDEC-compliant DDR SDRAM writes.

Internal command decoding coordinates power-down and refresh signals, helping DRAM retain data while reducing power consumption.

Odd-even clock sampling aligns DDR5 command and address timing, reducing skew, errors, and address-bus area under PVT variation.

Control signals cross from write to read clocks while parallel data is latched and serialized, improving throughput with segmented circuitry.

Packetized write and read control between base and core chips addresses stacked-memory interface complexity while supporting high-speed, error-aware transfer.

Separate read and write lines keep the write path inactive during reads, reducing power while preserving high-speed access in gain cell memory.

An output control circuit maps read bits to multiphase clocks, correcting out-of-phase sequencing and preserving burst order during serial output.

Sidewall defects in 3D cross-point arrays cause sneak and leakage currents; a higher-resistance shell directs current through the core.

Planar SRAM cells limit device density and increase chip area; BEOL transistor stacking packs more devices into the same footprint.

An HfB cap resists etching in magnetoresistance elements, reducing short-circuit defects in high-density memory cells.

Coordinating refreshes across victim rows helps mitigate electromagnetic coupling, memory errors, and data loss in dense memory arrays.

An MTJ-based reference circuit tracks temperature and process variations to position MRAM reference current for accurate data sensing.

Majority-bit analysis maps data to preferred cell states, helping non-volatile memory limit retention errors when state failure rates differ.

Address comparison identifies repeated-row accesses so a timing circuit can skip unnecessary bit-line pre-charging and reduce dynamic memory power.

Dual pulse generators align memory and pipeline clock signals to prevent hold-time failures and incorrect data transfer.

Truncating clock duration and applying a correction factor helps account for quantization errors when estimating memory-access cycles.

A comparator and delay circuit align read execution after cell discharge begins, reducing timing variation and read errors in magnetic memory.

Adjacent memory-cell columns share source lines to cut routing tracks and source-line resistance, increasing array density and simplifying read/write operations.

Assigning one common address to short-circuited wiring lines shares a drive signal, reducing redundant lines while preserving selective cell access.

Process, package, and PCB variation can shift LPDDR timing; iterative write-leveling calibration minimizes access-control phase error.

A dual-gate floating-body memory cell uses separate word and plate lines to limit channel-voltage variation and preserve operation margin.

Separate channel buffers and read-count address updates help a DMA circuit absorb latency mismatches and reduce congestion during multi-channel transfers.

When simultaneous deep trenching collapses fins, the LEDLED sequence fills first trenches before forming interleaved ones for denser, more reliable FeRAM.

A read-bit-line connection to the storage-transistor diffusion reduces 3T gain-cell leakage and extends data retention.

Matched etch selectivity in cell and peripheral mold insulation layers helps form consistent contact holes and reduce leakage currents.

A dielectric intermediary isolates word-line potential from transistor bodies while double gates reduce three-dimensional memory cell volume.

Tapered interfaces between buried and interlayer insulation help minimize voids and improve electrical connectivity in MTJ memory.

Voltage manipulation triggers the polymorphic latch to erase volatile-memory data instantly, without separate attack sensors or control logic.

A two-dimensional van der Waals free layer uses the spin Hall effect to switch magnetic moments at lower current density.

Conventional dual MTJ STT-MRAM cells can suffer reference-layer back-hopping; parallel magnetization stabilizes both layers and lowers write error rates.

Triplet supercurrents move magnetic domain walls along a racetrack, reducing Joule heat and energy use in non-volatile cryogenic memory.

Variable-thickness and crystalline dielectric layers let RRAM arrays support different endurance needs from one fabrication recipe, reducing process time and cost.

A 10T cell arrangement separates port paths and transistor contacts to simplify routing and support higher manufacturing yield.

Parallel refresh across multiple word lines allows semiconductor memory to add row-hammer refresh without degrading normal refresh timing.

Volatile memory stores upper and lower analog bounds, enabling faster reprogramming and scalable range matching for machine-learning CAM arrays.

A memory controller selects mitigation responses by row-activation intensity, balancing data protection against performance overhead.

Vertically stacked oxide-semiconductor layers use conductors and insulators to increase memory density per unit area.

A topological-metal Josephson junction modulates critical current by magnetic-field direction for fast, low-heat racetrack memory readout.

A current mirror copies MTJ cell current to the sense amplifier, improving signal margin and reading accuracy without precise timing control.

Memory devices without dedicated fault pins can encode error status in RDQS patterns or voltage levels for host detection.

Amorphous barriers limit grain growth in polycrystalline FeRAM layers, balancing total thickness with controlled grain size and improved induced current.

Step-pulse reset and set currents stabilize resistance transitions in phase-change memory cells, suppressing the double-hump effect for MLC storage.

Bypassing RRAM selector transistors forms a 0T1R array that reduces IR drop, write voltage, power use, and area overhead.

Two DRAM regions use separate algorithms, with a main protection table in the directly protected part to limit resource consumption.

High-capacitance bit lines waste dynamic power during ReRAM reads; partial discharge and differential sensing preserve reliable data detection.

Transistor variation can misread ferroelectric memory data; unity-gain inverter compensation aligns thresholds before sensing.