Memory Cell Array Circuit With Shared Source Lines for Lower Resistance
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within digital devices affects operating voltages and overall IC performance, particularly in memory macros, necessitating a solution to manage resistance variations.
Innovation Solution
A memory cell array design with shared source lines between adjacent columns of memory cells, reducing the number of source lines and corresponding routing tracks, thereby minimizing source line resistance and equalizing it with bit line resistance, which simplifies peripheral circuitry and increases memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of source lines is reduced by sharing between adjacent columns, then source line resistance is minimized and memory density is increased, but the complexity of routing and layout design increases
Solution Approach 1:
Adjacent columns of memory cells share common source lines, combining multiple source line functions into fewer shared lines. This merging reduces the total number of source lines required, thereby minimizing source line resistance and allowing for denser memory cell arrays while managing the complexity through systematic sharing patterns.
2Quantity of substance
If source line resistance is minimized through shared source lines, then memory density increases, but peripheral circuitry becomes more complex
Solution Approach 1:
The shared source lines are designed to serve multiple columns of memory cells simultaneously, making them universal conductive paths. This multi-functionality allows the same source line infrastructure to support more memory cells, increasing memory density while the systematic design of shared lines helps manage peripheral circuitry complexity through standardized interfaces.
3Stability of the object's composition
If conductive lines are optimized for resistance, then operating voltage stability improves, but manufacturing precision requirements increase
Solution Approach 1:
The design changes the topological parameters of the conductive line network by introducing shared source lines between adjacent columns. This parameter change fundamentally alters the resistance characteristics, allowing for better voltage stability across the memory array. The systematic sharing pattern provides predictable resistance characteristics that can be manufactured with standard precision tolerances.
Data Source
AI summary
A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a first source of a first selection transistor of a first memory cell of the second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the second column of memory cells.