Dual-Gate Floating-Body Memory Cell for Operation-Margin Control
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Solution Overview
Problem
Existing memory elements, such as dynamic flash memory cells, face challenges in maintaining operation margin and data retention characteristics due to variations in floating-body channel voltage and removal of signal electric charge, leading to the need for improved refresh operations.
Innovation Solution
A memory device with a semiconductor base material connected to impurity regions and gate conductor layers, where voltage control is used to manage hole accumulation and annihilation, and gate capacitances are designed to optimize page erase, write, and read operations, with parallel disposition of word and plate lines and vertical bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is applied to the select word line to perform read/write operations, then operation speed is improved, but variation in floating-body channel voltage increases causing operation margin decrease
Solution Approach 1:
A plate line is introduced as an intermediary between the word line and the memory cell gate. The plate line acts as a mediator that reduces direct capacitive coupling between the word line and the floating body, thereby suppressing voltage variation in the channel while still enabling effective gate control for read/write operations.
Solution Approach 2:
The gate control is segmented into two independent lines: the word line for selecting memory cells and the plate line for controlling the gate potential. This segmentation allows independent optimization of each line's function, enabling fast operation while maintaining stable channel voltage.
2Duration of action of stationary object
If holes are accumulated in the channel for data storage, then data retention is improved, but removal of some holes causes data retention characteristic decrease
Solution Approach 1:
The floating body structure provides automatic feedback control for data retention. The accumulated holes in the floating body create a feedback effect that maintains the stored state, while the dual-gate structure enables controlled removal of holes through the plate line without completely erasing the stored data, thus maintaining data retention characteristics.
3Reliability
If page erase operation is performed on selected pages, then data retention is improved, but power consumption increases
Solution Approach 1:
The page erase operation is applied locally to only the selected pages rather than the entire memory array. By controlling the plate line voltage selectively for specific pages, the erase operation is performed only where needed, reducing unnecessary power consumption while maintaining data retention for erased pages.
4Productivity
If multiple bit lines are operated simultaneously, then productivity is improved, but interference between bit lines increases
Solution Approach 1:
The bit lines are independently controlled through the floating body structure of each memory cell. The isolation provided by the floating body and the dual-gate configuration allows multiple bit lines to operate simultaneously with minimal interference, enabling parallel operations across multiple bit lines for improved throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances data retention characteristics and reduces power consumption while increasing operation speed by optimizing page erase, write, and read operations, allowing simultaneous operations on multiple bit lines.
Implementation Method 1
voltage of a floating-body channel of any selected memory cell connected to the select word line largely varies due to capacitive coupling between the gate electrode and the channel
Implementation Method 2
Among holes and electrons generated in a channel through an impact ionization phenomenon with source-drain current of a N-channel MOS transistor, some or all of the holes are held in the channel to write logical storage data '1'
Data Source
AI summary
A memory device is formed with at least one memory array, the memory array being formed with a plurality of pages and a plurality of bit lines, each page being formed with a plurality of memory cells arranged in a row direction on a substrate in a plan view, the plurality of memory cells being connected to the bit lines disposed in a column direction. Each of the memory cells included in each of the pages includes a semiconductor base material, a first impurity region and a second impurity region positioned in respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer. In the memory cell, the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first and second gate conductor layers is connected to a word line, and the other is connected to a plate line. A page erase operation, a page write operation, and a page read operation are performed by controlling a voltage applied to each of the source line, the bit line, the word line, and the plate line. At least one of the bit lines and one of the pages are selected in the page erase operation, the page write operation, and the page read operation, and an erase operation on the memory cell connected to both the bit line and the page thus selected, a write operation of storage data of the sense amplifier circuit to the memory cell, or a read operation from the memory cell to the sense amplifier circuit is executed.