3T Dynamic Gain Cell Layout for Reduced Gate Leakage
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Solution Overview
Problem
Modern integrated circuits face memory bottlenecks due to high latency and power consumption in off-chip DRAM access, with SRAM scaling difficulties and eDRAM reliability issues, particularly in advanced process technologies, leading to reduced data retention time and increased power overhead.
Innovation Solution
A three-transistor (3T) gain cell design with low gate leakage, where the read bit line is connected to the storage transistor diffusion, reducing gate leakage and extending data retention time, and incorporating a preset element to manage the storage node voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional 3T gain cell design is used, then the memory bitcell size is reduced compared to SRAM, but gate leakage increases causing faster deterioration of storage node voltage and limited data retention time
Solution Approach 1:
The patent inverts the conventional connection by connecting the read bit line (RBL) to the storage transistor diffusion instead of the read transistor diffusion. This inversion changes the leakage path and reduces gate leakage current, thereby extending data retention time while maintaining the compact 3T structure.
Solution Approach 2:
The patent converts the harmful gate leakage effect into a beneficial one by strategically connecting the RBL to the storage transistor diffusion. This configuration utilizes the transistor structure to reduce overall leakage current, transforming what would normally be a reliability issue into an advantage for data retention.
2Reliability
If frequent refresh cycles are implemented to maintain data in GCRAM, then data retention is improved, but power consumption increases significantly
Solution Approach 1:
The patent enables the gain cell to maintain its stored data for longer periods through the reduced gate leakage configuration, reducing its dependence on external refresh operations. The cell essentially serves itself by minimizing leakage through the innovative RBL connection, thereby reducing the power required for refresh cycles.
3Speed
If SRAM is used to ensure fast access and low power consumption, then access speed and power efficiency are improved, but die area increases significantly
Solution Approach 1:
The patent segments the functionality of traditional SRAM by using a 3T gain cell structure that separates the storage function from the access function more efficiently. This segmentation allows for reduced area while maintaining performance characteristics through the optimized transistor configuration and RBL connection.
Data Source
AI summary
A 3T gain cell includes a write transistor, a storage transistor and a read transistor. The write transistor has a first diffusion connected to a write bit line (WBL), a gate connected to a write word line (WWL) and a second diffusion. The storage transistor has a gate connected to said second diffusion of said write transistor, a first diffusion connected to a read bit line (RBL), and a second diffusion. The read transistor has a gate connected to a read word line (RWL) a first diffusion connected to said second diffusion of said storage transistor, and a second diffusion connected to a reference voltage.