Semiconductor Memory Refresh Control for Row-Hammer Timing
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in performing row-hammer refresh operations without degrading the performance of normal refresh operations, particularly due to constraints on refresh cycle times as memory capacity decreases.
Innovation Solution
A semiconductor memory device and control method that simultaneously perform normal refresh operations on multiple word lines in response to a single refresh request, allowing for both normal and row-hammer refresh operations to be completed within the specified refresh cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sequential refresh operations are performed on single word lines, then the refresh cycle time can be met, but the row-hammer refresh operation cannot be performed within the same cycle
Solution Approach 1:
The patent merges multiple single-word-line refresh operations into a single parallel refresh operation that simultaneously refreshes multiple word lines. By combining the refresh operations for multiple word lines into one coordinated action, the system completes what would traditionally require multiple sequential operations within a single refresh cycle time, thereby enabling both normal and row-hammer refresh operations to be performed together.
Solution Approach 2:
The patent dynamically adjusts the refresh operation mode based on detected hammer addresses. When hammer addresses are detected, the system transitions from traditional sequential single-word-line refresh to parallel multi-word-line refresh, enabling flexible adaptation to different operational conditions while maintaining timing constraints.
2Reliability
If row-hammer refresh operation is added to normal refresh operations, then data corruption is prevented, but the refresh cycle time is exceeded
Solution Approach 1:
The patent combines the row-hammer refresh operation with the normal refresh operation into a single integrated operation. Instead of performing them separately (which would exceed the refresh cycle time), the system merges them into one parallel operation that refreshes multiple word lines simultaneously, ensuring data integrity while completing within the specified time limit.
Solution Approach 2:
The system performs preliminary detection of hammer addresses and prepares the parallel refresh operation in advance. By detecting hammer addresses beforehand and pre-configuring the parallel refresh operation, the system ensures that the combined normal and row-hammer refresh operations can be executed together without exceeding the refresh cycle time.
3Reliability
If normal refresh operations are performed on all word lines sequentially, then all rows are refreshed, but the refresh cycle tREF is exceeded when row-hammer refresh is added
Solution Approach 1:
The patent merges multiple sequential refresh operations into a single parallel operation. By combining the refresh operations for multiple word lines into one coordinated action, the system refreshes all necessary rows while completing within the refresh cycle tREF, even when row-hammer refresh is included.
Solution Approach 2:
The system dynamically adjusts the refresh strategy based on hammer address detection. When hammer addresses are detected, it switches to parallel multi-word-line refresh mode, optimizing the refresh coverage and timing to ensure all rows are refreshed within the required cycle time tREF.
Data Source
AI summary
Provided are a semiconductor memory device and method for controlling the same, to carry out row-hammer refresh operations without degrading the performance of the normal refresh operation. The semiconductor device includes a control section 10 configured to simultaneously refresh each memory cell connected to a plurality of word lines in response to a refresh request, and performing a row-hammer refresh operation after executing at least one normal refresh operation.