Stack Memory Packet Communication for High-Speed TSV Transfer
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Solution Overview
Problem
Existing stack memory systems face challenges in achieving high-speed data transmission and efficient communication due to the design limitations of their physical interfaces, particularly in high bandwidth memory (HBM) systems.
Innovation Solution
The implementation of a stack memory device with a base chip and core chips connected via through-silicon vias (TSVs), incorporating a transmission/reception circuit, serialization/parallelization circuit, and data transmission control circuit to manage write and read operations using packets, ensuring synchronization and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a parallel data bus is used for data transmission, then data transmission speed is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces the traditional parallel data bus mechanical/electrical system with a serialization/parallelization circuit that converts parallel data into serialized packets for transmission through TSVs. This substitution reduces the physical interface complexity while maintaining high data transmission speeds through efficient packet-based communication.
Solution Approach 2:
The patent segments the data transmission process into discrete packets with headers containing control information. Each packet is independently processed by the base chip and core chips, allowing for modular handling of data transmission tasks and reducing overall system complexity.
2Productivity
If multiple core chips are stacked to increase memory capacity, then productivity is improved, but communication efficiency and data transmission reliability deteriorate
Solution Approach 1:
The patent implements feedback mechanisms through packet headers that contain control information and acknowledgment data. The base chip sends packets with control information to core chips, and core chips respond with status information, creating a closed-loop communication system that ensures reliable data transmission across multiple stacked chips.
Solution Approach 2:
The patent introduces packets as intermediary carriers for data transmission between the base chip and core chips. These packets serve as standardized intermediaries that encapsulate data, control information, and status data, facilitating reliable communication through the TSV interface despite the physical stacking complexity.
3Productivity
If serialization/parallelization circuit is implemented for packet-based communication, then device complexity increases, but data transmission efficiency and error detection capability improve
Solution Approach 1:
The serialization/parallelization circuit performs multiple functions: it converts parallel data to serialized packets for transmission, adds control information to packet headers, and enables error detection through structured packet formatting. This multi-functional circuit reduces the need for separate dedicated circuits for each function, justifying the complexity increase through consolidated functionality.
4Quantity of substance
If through-silicon vias (TSVs) are used to connect stacked chips, then memory capacity and integration density are improved, but manufacturing precision requirements and reliability challenges increase
Solution Approach 1:
The patent uses packets as intermediary data structures that travel through the TSV connection interface. By encapsulating data and control information in standardized packets, the system can tolerate certain variations in TSV alignment and connection quality, as the packet structure provides error detection and control mechanisms that compensate for manufacturing imperfections.
Data Source
AI summary
A stack memory device includes a base chip, and a core chip stacked with the base chip and electrically connected to the base chip. In the present disclosure, the base chip includes a transmission/reception circuit configured to receive write data, a write valid signal, and a transmission write clock signal, a serialization/parallelization circuit configured to receive the write data, based on the write valid signal in synchronization with the transmission write clock signal and to generate a parallelized input packet from the write data, and a data transmission control circuit configured to decode the parallelized input packet to extract first internal data that is stored in the core chip when a write operation is performed on the core chip from the parallelized input packet.