Pipe-Circuit Data I/O for Clock-Domain Crossing
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently performing data input/output operations due to the need for complex circuits to manage large data volumes, particularly in converting write and read clocks for domain crossing operations.
Innovation Solution
A data input/output device with a control circuit that generates input control signals synchronized with a write clock, performs domain crossing by converting it into a read clock, and generates output control signals, while a data input/output circuit latches parallel data and serializes it using these signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If complex circuits are used to manage large data volumes and perform domain crossing operations, then data transmission capacity is improved, but device complexity increases
Solution Approach 1:
The device is divided into distinct functional modules: a control circuit for clock domain crossing operations and a data input/output circuit for parallel-to-serial conversion. This segmentation allows each module to handle specific tasks efficiently, managing large data volumes without requiring a monolithic complex circuit architecture.
Solution Approach 2:
The control circuit acts as an intermediary between different clock domains, performing domain crossing operations on control signals. This intermediary approach enables data transmission between domains with different clock frequencies without requiring the entire system to operate at a single complex clock domain.
2Reliability
If domain crossing operation is performed to convert write clock to read clock, then clock synchronization is improved, but control signal generation complexity increases
Solution Approach 1:
The control circuit performs domain crossing operations on control signals in advance, before the actual data transmission occurs. By pre-synchronizing control signals between clock domains, the system ensures reliable clock synchronization without adding complexity to the real-time data path.
3Productivity
If parallel data is latched and serialized to generate output data, then data transmission efficiency is improved, but signal handling complexity increases
Solution Approach 1:
The data input/output circuit operates in periodic cycles, latching parallel data at specific intervals and then serializing it for output. This periodic operation pattern improves transmission efficiency by batching data operations, while the regular timing simplifies the control logic compared to continuous complex signal handling.
Data Source
AI summary
A data input/output device includes a control circuit configured to generate a plurality input control signals in synchronization with a write clock, to perform a domain crossing operation of converting a write clock into a read clock, and to generate a plurality of output control signals based on an output counting signal generated through the domain crossing operation, and a data input/output circuit configured to latch a plurality of pieces of internal data input in parallel in synchronization with the plurality of input control signals, and to serialize the latched plurality pieces of internal data to generate data in synchronization with the plurality of output control signals.