BEOL-Stacked SRAM Cell Structures for Higher Device Density
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Solution Overview
Problem
Existing SRAM cell implementations are limited by device density, which restricts chip area and increases fabrication costs due to planar surface area constraints.
Innovation Solution
The SRAM cells are formed in a back-end-of-line (BEOL) network, allowing transistors to be stacked rather than planar, reducing chip area requirements and lowering fabrication costs while providing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SRAM cells are implemented using planar structure, then fabrication process is simple, but device density is limited and chip area increases
Solution Approach 1:
The patent transitions from planar (2D) SRAM cell structure to a three-dimensional stacked structure where multiple transistor layers are vertically arranged. This dimensional change allows significantly more transistors to be packed into a smaller footprint, achieving higher device density without proportionally increasing chip area. The vertical stacking of transistor layers enables density multiplication while maintaining a compact planar footprint.
2Quantity of substance
If chip area is increased to accommodate more devices, then device density improves, but fabrication cost increases
Solution Approach 1:
By implementing vertical stacking of transistor layers, the patent achieves higher device density within the same chip area footprint. This eliminates the need to expand chip area to accommodate more devices, thereby avoiding the increased fabrication costs associated with larger chip areas while still achieving improved device density through three-dimensional integration.
3Quantity of substance
If transistors are stacked vertically, then device density increases and chip area reduces, but manufacturing complexity increases
Solution Approach 1:
The patent divides the SRAM cell structure into distinct transistor layers, with each layer containing specific transistor types (e.g., first transistor layer with first transistors, second transistor layer with second transistors). This segmentation allows for modular design and independent optimization of each layer while achieving vertical integration. The segmented structure simplifies the overall manufacturing process by enabling sequential fabrication of each transistor layer with dedicated access channels.
Solution Approach 2:
The patent introduces access channels as intermediary structures that connect different transistor layers vertically. These access channels serve as mediators that enable electrical connectivity between transistors in different layers without requiring complex interlayer routing. The access channels simplify the structural complexity by providing direct vertical pathways for signal and power transmission throughout the stacked transistor architecture.
Data Source
AI summary
An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the first direction; and a fourth n-channel layer engaged with a fourth gate layer to form a sixth device, the fourth gate layer coupled to a second word line and the fourth n-channel layer coupled to the third n-channel layer along the second direction.