ReRAM Differential Sensing Circuit with Partial Bit-Line Discharge
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Solution Overview
Problem
Existing ReRAM memory devices face high dynamic consumption during reading operations due to significant capacitance of bit lines, leading to inefficiencies and potential reading errors.
Innovation Solution
A ReRAM device with a reading circuit that includes a lock-type detection amplifier and control circuit for reduced bit line discharge, utilizing partial discharge phases and isolation transistors to minimize dynamic consumption and improve reading reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit lines are fully discharged from pre-charge value to reference voltage during reading operation, then reading speed is improved, but dynamic power consumption increases due to significant bit line capacitance
Solution Approach 1:
The patent applies partial discharge by only discharging the bit line to an intermediate voltage level (e.g., VDD/2) rather than fully discharging to the reference voltage level. This partial action reduces the voltage swing and associated capacitive charging/discharging current, thereby lowering dynamic power consumption while still enabling sufficient signal differentiation for reliable reading.
Solution Approach 2:
The patent changes the voltage parameter by introducing an intermediate discharge voltage level instead of using the full voltage range. The bit line is discharged to this intermediate level (e.g., VDD/2) during the reading operation, which modifies the electrical parameters to reduce power consumption while maintaining reading functionality.
2Use of energy by moving object
If bit line discharge is minimized to reduce dynamic consumption, then power consumption is improved, but reading reliability may deteriorate due to reduced voltage difference
Solution Approach 1:
The patent introduces an intermediate voltage level (e.g., VDD/2) as a mediator between the pre-charge voltage (VDD) and reference voltage (GND). This intermediate level serves as a discharge target that reduces power consumption while the differential sensing amplifier still can't distinguish between the two resistive states due to the maintained voltage difference.
Solution Approach 2:
The reading circuit is designed to perform multiple functions: it can operate with partial discharge to reduce power consumption, and it maintains the ability to reliably distinguish between HRS and LRS states through differential sensing. The circuit universally handles both power-efficient operation and reliable data detection.
3Speed
If full discharge of bit lines is performed, then reading operation speed is improved, but harmful factors increase due to high current flow and potential disturbance to other cells
Solution Approach 1:
The patent applies partial discharge by only discharging the bit line to an intermediate voltage level (e.g., VDD/2) rather than fully discharging to the reference voltage level. This partial action reduces the voltage swing and associated capacitive charging/discharging current, thereby lowering dynamic power consumption while still enabling sufficient signal differentiation for reliable reading.
Solution Approach 2:
The patent converts the potentially harmful full discharge current into a beneficial partial discharge current. By intentionally limiting the discharge to an intermediate level, the design transforms what would be a harmful high-current event into a controlled, low-power operation that still achieves reliable reading through differential sensing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces dynamic consumption and enhances reading reliability by minimizing bit line discharge, ensuring accurate data output and reduced power usage during read operations.
Implementation Method 1
a lock-type detection amplifier formed of cross-connected inverters and provided with a first reading node and a second reading node... allows direct comparison of currents flowing through the resistive elements and circulating via bit lines
Implementation Method 2
During such an operation, the nodes of a cell connected to the bit lines discharge by typically passing from a pre-charge value corresponding to a supply voltage VDD to a reference voltage GND or vice versa. This discharge depends on the capacitance of the bit lines which is significant and leads to high consumption.
Data Source
Figure 1~2
Figure 3
Figure 4~5B
AI summary
Resistive random access memory (ReRAM) comprising: - a matrix (M1) of cells (Cij) each connected to a first supply line (SL) set at a first supply potential, each cell having a resistive element (1, 2) and a selection transistor (Ms1, Ms2), - a read circuit (400) associated with a given row of cells and comprising a latching type detection amplifier (440) connected to a second supply line (45) set at a second supply potential, the device further comprising: - a control circuit for the read operations configured so that during a read: - apply to said first bit line (BL0) a potential equal to said first supply potential (GND, VDD) while isolating the first bit line (BL0) from said detection amplifier (440), then, - couple the first bit line (BL0) to said detection amplifier (440).