Gain Cell Memory With Separate Read/Write Lines for Lower Power
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Solution Overview
Problem
Existing gain cell memories face challenges in reducing power consumption, particularly during read operations due to the activation of both read and write word lines, which increases power consumption even in read-only operations.
Innovation Solution
The gain cell memory employs separate word lines and bit lines for reading and writing, allowing non-destructive reading and minimizing the activation of the write word line during read operations, and includes a detection circuit to latch and transmit data without inverting it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate word lines and bit lines are used for reading and writing, then power consumption is reduced during read operations, but device complexity increases
Solution Approach 1:
The patent divides the memory device into separate read and write circuits with dedicated word lines (first word line for read, second word line for write) and bit lines (first bit line for read, second bit line for write). This segmentation allows independent control of read and write operations, enabling the write circuit to remain inactive during read operations, thereby reducing power consumption while maintaining functional complexity through specialized circuit blocks.
2Adaptability or versatility
If the write word line is activated during read operations, then data writing capability is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic control where the first word line (read) and second word line (write) are independently activated based on operation type. During read operations, only the first word line is activated while the second word line remains inactive, and vice versa for write operations. This dynamic switching capability allows the device to adapt to different operation modes, reducing power consumption by deactivating unnecessary circuits while maintaining full write capability when needed.
3Volume of moving object
If gain cell memory structure is used without capacitors, then device miniaturization is enabled, but data retention challenges arise
Solution Approach 1:
The patent replaces the traditional capacitor-based data storage mechanism with a gain cell memory structure that uses transistor gate voltage states to represent data. Instead of relying on physical charge storage in capacitors, the invention uses the electrical state of transistors (on/off states controlled by gate voltages) to encode and retain data. This substitution eliminates the need for capacitor components, enabling device miniaturization while maintaining data retention through the stable voltage states of the transistor gates.
Data Source
AI summary
A memory includes a first data-line and a first control-line for writing and a second data-line and a second control-line for reading. A memory cell includes a first transistor connected to the first control-line at a gate and connected to the first data-line, a second transistor connected to the second control-line at a gate and connected to the second data-line, and a third transistor connected to the first transistor at a gate and connected to the second transistor. A detector is connected to the first and second data-lines. In writing or reading, the controller activates the second control-line, the detector detects first data based on a voltage of the second data-line, and thereafter the controller activates the first control-line. After reception of a write command, the detector transmits second data from outside to the gate of the third transistor when latching the second data.