DRAM Memory Layout for Compact Row-Hammer Protection
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Solution Overview
Problem
The increasing capacity and reduced geometry of dynamic random access memories (DRAM) exacerbate the row-hammering effect, making existing preventive refresh methods less effective and resource-intensive.
Innovation Solution
A memory device architecture that divides DRAM circuits into a directly protected part and an indirectly protected part, using two algorithms to manage the row-hammering effect, with a main table stored in the directly protected part to optimize resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory device capacity is increased, then the storage capability is improved, but the size of the protection tables must be increased which consumes more resources
Solution Approach 1:
The patent divides the memory device into multiple sub-banks, each with its own independent protection table. This segmentation allows the total protection resources to be distributed across sub-banks rather than requiring a single large table, thereby managing large-capacity memory while controlling resource consumption at each sub-bank level.
2Manufacturing precision
If the geometry is reduced to increase density, then the manufacturing precision is improved, but the scope of row-hammering effect increases affecting more rows
Solution Approach 1:
By dividing the memory into sub-banks with independent protection mechanisms, the patent limits the propagation of row-hammering effects within each sub-bank. This segmentation contains the harmful effects to smaller scopes, preventing them from affecting the entire memory device even when geometry is reduced and density is increased.
Solution Approach 2:
The patent introduces intermediate protection tables at the sub-bank level that act as mediators between the physical memory rows and the control logic. These intermediate structures enable independent management of row activations and prevent cascading effects across the entire memory device.
3Reliability
If the critical hammering value is lowered to protect against finer patterns, then the reliability is improved, but the tables must be updated more frequently increasing resource usage
Solution Approach 1:
The patent distributes the burden of frequent table updates across multiple sub-banks, each with its own protection table. This segmentation allows the system to maintain low critical hammering values for reliability while spreading the resource consumption of frequent updates across independent sub-banks, preventing any single sub-bank from being overwhelmed.
Data Source
AI summary
The invention relates to a memory device comprising:—DRAM memory circuits (100), the total capacity of which is divided into a first part (102) and a second part (103) larger than the first part (102);—a control circuit configured to access the memory circuits, the control circuit comprising:—a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect;—a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from a row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).