Self-Destructive Polymorphic Latch for Instant Volatile-Memory Erasure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing countermeasures for protecting sensitive information in volatile memory against active physical attacks, such as voltage tampering, are unreliable, costly, and can be easily disabled by attackers, failing to provide immediate data destruction.
Innovation Solution
A self-destructive polymorphic latch that integrates attack detection and response into the circuit, changing its behavior with supply voltage manipulation to automatically erase data when under attack, utilizing polymorphic gates and registers that switch functionality between NOR and NAND operations based on threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sensors are used to detect physical attacks and trigger destruction, then data protection is achieved, but the response time is slow (thousands of clock cycles) and the circuitry can be identified and disabled by attackers
Solution Approach 1:
The patent merges the detection and destruction functions into a single integrated polymorphic latch circuit. The latch simultaneously detects voltage anomalies through its polymorphic behavior and executes data destruction through its feedback mechanism, eliminating the need for separate sensors and control logic. This integration reduces response time to instantaneous while maintaining protection reliability.
Solution Approach 2:
The polymorphic latch performs self-detection and self-destruction without external intervention. When voltage manipulation occurs, the latch automatically detects the anomaly through its voltage-dependent polymorphic behavior and triggers self-destructive feedback to erase stored data, eliminating the need for external sensors and control systems.
2Ease of operation
If separate detection and destruction circuitry is used, then functional separation is achieved, but the circuitry can be identified and disabled by attackers
Solution Approach 1:
The patent combines detection and destruction functions into a single polymorphic latch, eliminating separate circuitry that could be identified and disabled by attackers. The unified circuit performs both functions through its inherent polymorphic behavior and feedback mechanism, making it resistant to attack while maintaining operational functionality.
3Loss of time
If polymorphic gates are used to change behavior with voltage manipulation, then immediate data erasure is achieved, but the circuit complexity increases
Solution Approach 1:
The polymorphic latch circuit performs multiple functions using a unified structure: it stores data normally, detects voltage anomalies through polymorphic behavior, and executes data destruction through feedback. This multi-functionality reduces the need for separate circuits while achieving immediate data erasure, balancing complexity with functionality.
4Reliability
If traditional memory protection mechanisms are used, then data security is maintained during normal operation, but the mechanisms fail during active physical attacks
Solution Approach 1:
The polymorphic latch dynamically changes its behavior based on supply voltage conditions. During normal operation, it functions as a standard data storage latch. During attacks, its polymorphic behavior detects voltage manipulation and triggers self-destructive feedback to erase data, providing adaptability to different operational states and attack conditions.
Data Source
AI summary
A polymorphic latch comprising a pair of polymorphic gates that is configured in a D-latch, wherein a polymorphic gate of the pair of polymorphic gates comprises (i) a low voltage function and a high voltage function, (ii) a pull-down network (PDN) that is associated with the high voltage function, (iii) a pull-up network (PUN) that is coupled to the PDN, wherein the PUN is associated with the low voltage function, and (iv) one or more gating transistors that are configured to provide the PDN with a path to a ground; a pair of AND logic gates, wherein an output of an AND logic gate of the pair of AND logic gates is coupled to an input of the polymorphic gate; and an inverter coupled to an input of the AND logic gate.