Multiphase Read Data Arrangement for Correct Burst Sequencing
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Solution Overview
Problem
Semiconductor memories experience out-of-sequence read data due to clocking operations that are out-of-phase, leading to synchronization issues and delayed access times, which are challenging to resolve without causing timing inaccuracies.
Innovation Solution
Implementing a data register with a multiplexer control circuit that rearranges read data based on multiphase clocks to synchronize data output, ensuring correct sequencing and burst order, even in out-of-phase clocking scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If out-of-phase clocking is used to generate multiphase clocks, then clock frequency multiplication is achieved, but read data output sequence becomes incorrect
Solution Approach 1:
The patent applies preliminary action by detecting the phase relationship between external and internal clocks before data output operations occur. The control circuit identifies whether clocking is in-phase or out-of-phase in advance, and pre-configures the data output circuit accordingly to ensure correct sequencing. This proactive detection and configuration prevents sequence errors before they manifest in the output data.
Solution Approach 2:
The patent implements feedback by continuously monitoring the phase relationship between external and internal clocks. The control circuit receives feedback signals indicating whether the system is operating in in-phase or out-of-phase mode, and automatically adjusts the data output circuit configuration based on this feedback. This closed-loop control ensures that the data output sequence remains correct regardless of the clocking mode being used for frequency multiplication.
2Manufacturing precision
If clock swapping is performed to preserve synchronization, then data sequencing is maintained, but access times are delayed
Solution Approach 1:
The patent eliminates the need for time-consuming clock swapping by performing preliminary detection of the clock phase relationship. The control circuit identifies the clocking mode in advance and pre-configures the data output circuit to handle out-of-phase operations correctly. This approach maintains data sequencing accuracy without introducing the delays associated with synchronous clock swapping operations.
Solution Approach 2:
The patent introduces a control circuit as an intermediary between the clock generation system and the data output circuit. This intermediary detects the phase relationship and automatically configures the data output circuit to compensate for out-of-phase clocking effects. By using this intermediary control mechanism, the system maintains correct data sequencing without requiring physical clock swapping, thereby avoiding access time delays.
3Stability of the object's composition
If synchronous clock swapping is implemented to maintain synchronization, then clock alignment is preserved, but timing inaccuracies occur
Solution Approach 1:
The patent uses feedback to continuously monitor the phase relationship between external and internal clocks and automatically adjusts the data output circuit configuration based on detected conditions. This feedback mechanism maintains clock synchronization stability while avoiding the timing inaccuracies introduced by synchronous swapping operations, as the system adapts to the clocking mode without requiring disruptive clock changes.
Solution Approach 2:
The control circuit acts as an intermediary that detects clock phase relationships and configures the data output circuit accordingly. This intermediary approach preserves clock synchronization stability while eliminating the timing inaccuracies associated with synchronous clock swapping, as the phase detection and circuit configuration occur without disrupting the clock signals themselves.
Data Source
AI summary
Apparatuses and methods for arranging read data for output are described. An example apparatus includes a clock circuit, a data output circuit, and a control circuit. The clock circuit is configured to provide multiphase clock signals having different phases from each other based on a clock signal. The data output circuit is configured to receive a plurality of read data bits responsive to a read command and serially output each of the plurality of read data bits in synchronism with a corresponding one of the multiphase clock signals. The control circuit is configured to determine the correspondences between the plurality of read data bits and the multiphase clock signals based on information about which of the multiphase clock signals captures the read command.