Double-Gate Memory Cells for Word-Line Potential Isolation
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in minimizing the volume of memory cells while effectively isolating the potential of word lines from affecting the body potential of neighboring transistors, leading to inefficiencies in transistor performance.
Innovation Solution
The memory device employs a double-gate structure for transistors, where a semiconductor is sandwiched between conductors acting as word lines and backgates, with shared conductors between transistors along the z-axis, allowing for a reduced interval between semiconductors and minimizing cell volume while maintaining effective potential isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a conventional three-dimensional memory cell structure is used, then the memory cell volume can be reduced, but the word line potential interferes with the body potential of neighboring transistors
Solution Approach 1:
An insulating film is introduced as an intermediary layer between the word line conductor and the transistor body. This insulating film acts as a mediator that electrically isolates the word line potential from the transistor body, preventing potential interference while maintaining the compact three-dimensional memory cell structure.
Solution Approach 2:
The memory cell structure is segmented into distinct functional regions with clear electrical isolation. By dividing the structure into separate components (conductor, insulating film, transistor body) with defined boundaries, the patent achieves both compact volume and effective potential isolation between neighboring elements.
2Volume of moving object
If the interval between semiconductors is reduced to minimize cell volume, then memory cell volume decreases, but potential cross-talk between neighboring transistors increases
Solution Approach 1:
The insulating film serves as a protective intermediary that enables closer spacing of semiconductor structures. By introducing this dielectric barrier, the patent achieves reduced interval between semiconductors while maintaining reliable electrical isolation, thus preventing potential cross-talk between neighboring transistors.
Solution Approach 2:
The patent addresses the spacing issue by introducing an additional dimensional layer (the insulating film layer) between existing structures. This vertical dimensionality addition allows horizontal proximity of semiconductors while maintaining electrical isolation through the intermediate insulating layer.
Data Source
AI summary
A first insulator is on a surface of the first semiconductor on a side of a second direction crossing the first direction. A first conductor is on a surface of the first insulator on the side of the second direction. A second insulator is on a surface of the first semiconductor on a side of a third direction opposite to the second direction. A second semiconductor is located further in the third direction than the first semiconductor. A third insulator is on a surface of the second semiconductor on the side of the third direction. A second conductor is on a surface of the third insulator on the side of the third direction. A fourth insulator is on a surface of the second semiconductor on the side of the second direction. A third conductor is in contact with the second insulator and the fourth insulator.