Multi-Channel DMA Circuit Buffer Arbitration for Latency Congestion
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Solution Overview
Problem
DMA circuits face performance issues due to varying latency between data sources and destinations, leading to data transmission congestion when multiple channels are involved.
Innovation Solution
A DMA circuit with a buffer circuit, channels, write status determination, read address generation, and control circuit that manages read and write requests to optimize data transfer by arbitrating and updating addresses to handle multiple channels efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission is performed between multiple channels in a DMA circuit, then the data transfer capability is improved, but congestion occurs due to varying latency and speed mismatches between data sources and destinations
Solution Approach 1:
The patent segments the data transmission process by introducing separate buffer circuits for each channel (first buffer circuit for first channel, second buffer circuit for second channel). This segmentation isolates the data streams of different channels, preventing congestion from propagating across channels while maintaining high data transfer capability. Each buffer circuit independently manages its channel's data with its own start address and read count, ensuring stable and reliable transmission.
2Adaptability or versatility
If the read/write speed of data source does not match the read/write speed of data destination, then flexibility in handling different devices is improved, but latency becomes variable and unpredictable
Solution Approach 1:
The patent implements preliminary action by pre-allocating buffer circuits and pre-calculating start addresses for each channel before data transmission begins. The write status determination circuit determines start addresses in advance based on buffer circuit states, and the read address generation circuit pre-generates read addresses using the formula: read address = start address + read count. This preliminary preparation eliminates variable latency during actual data transfer, while the buffer circuits absorb speed mismatches between data sources and destinations.
3Device complexity
If multiple channels share the same buffer circuit, then device complexity is reduced, but data transmission congestion occurs due to latency variations
Solution Approach 1:
The patent resolves the contradiction by transitioning from a shared buffer resource (one-dimensional contention) to separate buffer resources (multi-dimensional parallelism). By providing dedicated buffer circuits for each channel, the system moves from sequential access to parallel access across channels. This dimensional change eliminates congestion while maintaining manageable complexity through modular buffer circuit design that can be replicated for additional channels.
Data Source
AI summary
An operation method of a direct memory access (DMA) circuit comprising a buffer circuit and two channels includes following steps: determining first and second start addresses from the buffer circuit respectively according to first and second read requests of first and second channels that respectively correspond to first and second data; determining a read address according to the first start address and a read count; reading a first part of the first data from the buffer circuit according to the read address and updating the read count; reading at least one part of the second data from the buffer circuit according to the second start address after reading the first part of the first data; updating the read address according to the first start address and the updated read count; and reading a second part of the first data from the buffer circuit according to the updated read address.