LPDDR PHY Write-Leveling Calibration for Access-Control Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for calibrating access control signals in low power double data rate (LPDDR) memory devices fail to account for process, package, and PCB variations, leading to inconsistent phase errors and reduced yield in mass production.
Innovation Solution
A physical layer circuit with a write leveling training circuit and method that uses a clock generator and TX logic to generate control clocks, coupled with a scan signal controller and phase control circuit to minimize phase errors between memory clocks and access control signals through iterative calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If simulation-derived parameters are applied to all chips, then design consistency is maintained, but manufacturing yield deteriorates due to process, package, and PCB variations
Solution Approach 1:
The patent implements a preliminary calibration action during the manufacturing process where each chip's actual phase error is measured and compensated before the chip is shipped. The write leveling training circuit performs this calibration by adjusting the phase of access control signals based on measured phase errors, ensuring each chip is pre-adjusted to optimal performance for its specific process, package, and PCB variations.
Solution Approach 2:
The patent changes the phase parameter of access control signals dynamically during calibration. The write leveling training circuit adjusts the phase of write clock signals and data strobe signals based on measured phase errors, transforming a static simulation-derived parameter approach into a dynamic, chip-specific parameter adjustment that compensates for manufacturing variations.
2Device complexity
If no calibration circuit is added, then device complexity is minimized, but phase error detection and correction capability is lost
Solution Approach 1:
The patent implements a self-service calibration mechanism where the memory device calibrates its own phase errors using integrated write leveling training circuits. The calibration function is built into the device itself, eliminating the need for external calibration equipment and enabling automatic phase error detection and correction during the manufacturing process.
Solution Approach 2:
The patent implements a feedback mechanism where the phase error measurement result is fed back to the write leveling training circuit, which then adjusts the phase of access control signals accordingly. This closed-loop feedback system enables continuous optimization of signal timing until phase errors are minimized.
3Measurement precision
If iterative calibration is performed, then phase error precision is improved, but calibration time increases
Solution Approach 1:
The patent implements periodic action through iterative calibration cycles where the write leveling training circuit repeatedly measures phase errors and adjusts signal phases in discrete steps. Each iteration refines the phase alignment, and the process continues until convergence criteria are met, balancing precision requirements with time constraints.
Data Source
AI summary
A physical layer (PHY) circuit, a write leveling training circuit and a method for calibrating an access control signal are provided. The PHY circuit includes the write leveling training circuit, a clock generator and a transmitting (TX) logic. The write leveling training circuit generates at least one phase control signal. The clock generator outputs at least one control clock according to the phase control signal. The TX logic generates the access control signal according to the control clock, wherein a phase of the access control signal is associated with the phase control signal. The memory device outputs a data signal according to a phase error between a memory clock and the access control signal, and the write leveling training circuit determines a target value of the phase control signal according to the data signal, in order to minimize the phase error between the memory clock and the access control signal.