DDR SDRAM Data Strobe Logic Adjustment for JEDEC Compliance
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Solution Overview
Problem
DDR SDRAM data strobe signals that do not follow the JEDEC standard can cause malfunctions, leading to failed data write operations.
Innovation Solution
A control unit with multiple input and output stages that adjust logic states based on the identity of input signals, allowing it to regenerate or follow the data strobe signals, ensuring compliance with the JEDEC standard even when signals have the same value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data strobe signal follows the JEDEC standard with complementary logic states, then the DDR SDRAM operates reliably, but the system cannot accept non-compliant signals that have the same logic value on both lines
Solution Approach 1:
A control unit is introduced as an intermediary between the external data strobe signal source and the DDR SDRAM internal circuitry. This control unit receives the incoming data strobe signals on complementary lines, compares their logic states, and generates appropriate internal clock signals. When signals are non-compliant (same logic value), the control unit detects this condition and generates valid complementary clock signals anyway, thereby mediating between non-compliant external signals and the memory's requirement for standardized signals.
Solution Approach 2:
The control unit monitors the logic state parameters of the incoming data strobe signals and dynamically adjusts its output behavior based on the detected parameter values. When both input signals have the same logic value (0 or 1), the control unit changes its operation mode to generate forced complementary output signals, thereby transforming the parameter relationship from non-compliant to compliant while maintaining signal integrity.
2Adaptability or versatility
If the control unit accepts non-compliant data strobe signals with identical logic values, then signal compatibility improves, but the risk of malfunction increases without signal validation
Solution Approach 1:
The control unit implements a feedback mechanism by continuously monitoring the logic states of the incoming data strobe signals and using this information to control its output signal generation. The unit compares the logic values on both complementary lines and uses this feedback to determine whether to operate in normal pass-through mode or in forced complementary generation mode, thereby ensuring reliable operation while accepting various input signal types.
Solution Approach 2:
The control unit dynamically adjusts its signal processing behavior based on the real-time state of the input signals. It transitions between different operational modes: when inputs are compliant, it passes them through; when inputs are non-compliant with identical logic values, it dynamically switches to generating forced complementary signals. This dynamic adaptation allows the system to maintain reliability across varying signal conditions.
3Reliability
If the control unit regenerates complementary signals for non-compliant inputs, then signal compliance is ensured, but the circuit complexity increases
Solution Approach 1:
The control unit is segmented into distinct functional modules: an input stage with comparison logic that detects signal compliance, a control logic unit that determines the appropriate operational mode, and an output stage that generates either pass-through or forced complementary signals. This segmentation allows each module to perform its function independently and efficiently, reducing overall circuit complexity while ensuring signal compliance.
Data Source
AI summary
A control unit in a memory and a method of controlling a memory are provided. The control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processed signal. The second output stage is connected to the second input stage and configured to generate a second processed signal. If the first signal and the second signal are identical, the first processed signal and the second processed signal are different.