Memory Circuit Row Detection for Skipping Bit-Line Pre-Charging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The power consumption associated with bit line pre-charging in memory devices is significant and adversely impacts performance as devices scale down.
Innovation Solution
A memory circuit that skips one or more pre-charging steps based on the locations of subsequently accessed memory cells, utilizing a comparator to determine if the addresses of the memory cells indicate the same row, and a timing circuit to control pre-charging accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit line pre-charging is performed for every memory access, then reliable data access is ensured, but dynamic power consumption increases significantly
Solution Approach 1:
The patent implements a pre-charging skip mechanism that detects when consecutive memory accesses target the same bit line and skips the pre-charging operation in those cases. The control circuit monitors address signals and generates a skip signal when the same bit line is accessed consecutively, allowing the memory device to rush through the access cycle without the power-consuming pre-charging step while maintaining data access reliability.
Solution Approach 2:
The patent changes the operational parameters of the bit line pre-charging circuit by introducing a controllable enable signal that dynamically adjusts whether pre-charging occurs. Based on the detected access pattern (same bit line consecutive access), the system modifies the pre-charging parameter from active to inactive state, thereby reducing power consumption while preserving reliable data access when needed.
2Use of energy by moving object
If pre-charging operations are minimized to reduce power consumption, then dynamic power is reduced, but data access reliability may be compromised
Solution Approach 1:
The patent employs a feedback mechanism where the control circuit continuously monitors memory access patterns and uses this information to dynamically control pre-charging operations. The system receives feedback from address signal comparisons and adjusts the pre-charging enable signal accordingly, ensuring that pre-charging is performed only when necessary for data access reliability while minimizing unnecessary pre-charging operations that consume power.
Solution Approach 2:
The patent introduces dynamic control over the pre-charging operation through a timing circuit that adapts its behavior based on real-time access patterns. The system transitions from a static always-on pre-charging approach to a dynamic conditional approach, where the pre-charging circuit is enabled or disabled based on detected access patterns, thereby maintaining reliability while reducing power consumption.
Data Source
AI summary
A memory circuit includes a memory array including a plurality of memory cells, wherein each of the plurality of memory cells is accessible through a plurality of bit lines, a comparator configured to receive a first address signal indicating a first row along which a first one of the memory cells is disposed and a second address signal indicating a second row along which a second one of the memory cells is disposed, and generate a control signal with a logic state indicating whether the first row is identical to the second row, a timing circuit configured to skip pre-charging the bit lines of the second memory cell after accessing the first memory cell, based on the logic state of the control signal.