Memory Cell Voltage Supply Structure With Fewer Global Switches
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Solution Overview
Problem
Existing semiconductor devices face challenges in optimizing the area margin in peripheral regions due to the complexity and number of global switches required for voltage supply structures, which affects the miniaturization and efficiency of memory cells.
Innovation Solution
A voltage supply structure that includes a current direction control circuit and a reduced number of global switches, utilizing a single global switch to connect a global line and a local line based on address signals, and local switches to connect bit and word lines, allowing forward and reverse currents to flow through memory cells based on data direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple global switches are used to supply voltage to memory cells, then voltage supply reliability is improved, but device area increases
Solution Approach 1:
The patent combines multiple global switch functions into a single global switch by introducing a local switch at each memory cell. The global switch controls voltage supply to multiple local switches, which then individually control voltage supply to their respective memory cells. This merging reduces the number of global switches from multiple to one, thereby reducing device area while maintaining voltage supply reliability through the distributed local switch architecture.
Solution Approach 2:
The patent segments the voltage supply control function by dividing it into global switch control and local switch control. The global switch handles coarse-grained voltage supply control to groups of memory cells, while local switches handle fine-grained control at individual memory cell levels. This segmentation allows reduction of global switch count while maintaining comprehensive control coverage through the hierarchical structure.
2Area of stationary object
If the number of global switches is reduced to secure area margin, then device area is reduced, but voltage supply control complexity increases
Solution Approach 1:
The control complexity is segmented between global switch control logic and local switch control logic. The global switch receives control signals for group-level voltage supply, while local switches receive control signals for individual cell-level voltage supply. This segmentation distributes the control complexity across different levels of the hierarchy, making the overall system more manageable despite the added local control functions.
Solution Approach 2:
The patent introduces a hierarchical dimension to the voltage supply control structure, with global switches operating at one level and local switches operating at another level. This dimensional change from a flat switch architecture to a hierarchical switch architecture allows reduction of global switch count while distributing control functions across multiple levels, thereby managing complexity through structural organization.
3Manufacturing precision
If local switches are added at each memory cell, then voltage supply precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by placing a dedicated local switch at each memory cell or small group of memory cells. Each local switch provides precise voltage supply control tailored to its specific local region, enabling fine-grained voltage control for operations such as read, write, and erase. This local quality approach improves voltage supply precision by ensuring each memory cell receives appropriately controlled voltage, while the distributed nature of local switches allows modular implementation that manages overall device complexity.
Data Source
AI summary
A voltage supply structure may include a first global switch that connects a global positive line and a local positive line in response to a first common address signal, a first local column switch that connects the local positive line and a bit line in response to a first local column address signal, a first local row switch that connects the local positive line and a word line in response to a first local row address signal, and a memory cell connected between the bit line and the word line.